Multilayered printed circuit board and manufacturing method thereof

ABSTRACT

An opening is formed in resin  20  by a laser beam so that a via hole is formed. At this time, copper foil  22 , the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening  20   a  can be formed in the resin  20  if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin  20  which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/875,486, filed Oct. 19, 2007, the entire contents of which isincorporated here by reference. U.S. application Ser. No. 11/875,486 isa Divisional of U.S. application Ser. No. 10/356,464 filed Feb. 3, 2003(U.S. Pat. No. 7,415,761), which is a Divisional of U.S. applicationSer. No. 09/797,916 filed Mar. 5, 2001 (U.S. Pat. No. 6,591,495), whichis a Continuation of PCT Application No. PCT/JP99/04142 filed Jul. 30,1999, and claims the benefit of priority under 35 USC §119 to JapanesePatent Application Nos. 10-249382 filed Sep. 3, 1998, 10-281940 filedSep. 16, 1998, 10-281942 filed Sep. 16, 1998, 10-303247 filed Oct. 9,1998, 11-043514 filed Feb. 22, 1999, 11-043515 filed Feb. 22, 1999,11-060240 filed Mar. 8, 1999, and 11-116246 filed Apr. 23, 1999.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayered printed circuit boardand a manufacturing method therefor, and more particularly to a methodof manufacturing a multilayered printed circuit board with which anopening is formed by using laser beam and by forming a plated film inthe opening to form a via hole, an opening in a solder-resist layer andan opening for forming a through hole. The present invention relates tothe structure of a substrate which is a core.

2. Background Art

A method of manufacturing a multilayered printed circuit board has beensuggested in Japanese Patent Laid-Open No. 9-130038 which uses aso-called conformal mask such that a conductive layer is formed on thesurface of an insulating resin layer. Moreover, an opening is formed ina portion of the conductive layer by etching, followed by irradiatingthe opening with a laser beam to form an opening in the insulating resinlayer.

The foregoing technique, which uses a thick copper film having athickness of 12 mm to 18 mm as the conformal mask, encounters a largethermal conductivity, causing heat to easily be dispersed. Hence itfollows that a high output laser beam or a pulse-shape laser beam mustbe applied a multiple of times. Therefore, when the opening is formed inthe insulating resin layer, undercut occurs with which the opening iswidened in the lateral. If a via hole is formed by applying anelectrolytic copper plated film and an electroless copper plated film tothe opening, separation of the electrolytic copper plated film and theelectroless copper plated film easily occurs. As a result, reliabilityin the connection has been unsatisfactory.

To a worse extent, the foregoing technique cannot form a conductivecircuit having fine pitch. In the manufacturing process, the electrolesscopper plated film (0.1 μm to 5 μm) and the copper foil (12 μm to 18μ m)under the resist must be removed after the electrolytic copper platedfilm has been performed. Therefore, the width of the conductive circuitcannot be reduced.

Since the thick copper foil is employed as the conformal mask, a viahole having a small diameter cannot be formed. In the manufacturingprocess, the electroless copper plated film (2 μm) and the copper foil(12 μm to 18μ m) under the resist must be removed, the diameter of thevia hole cannot easily be reduced.

To solve the foregoing problems, an object of the present invention isto suggest a multilayered printed circuit board which is capable ofpreventing occurrence of undercut if a conformal mask is employed.

A method disclosed in Japanese Patent Publication No. 4-3676 and using a“conformal mask” has the steps of previously forming a metal layer on aninsulating resin layer; etching and removing the metal layer in theportion in which a via hole will be formed; and irradiating the openingwith a laser beam so that only the insulating resin layer exposedthrough the opening is removed. The foregoing technique, which iscapable of forming a plurality of via holes in the insulating resinlayer, exhibits satisfactory productivity.

However, studies performed by the inventor of the present invention haveresulted in resin which is left in the opening for forming the via hole,causing the residual resin to expand and unsatisfactorily move the viahole in the upward direction. Thus, there arises a problem in that theupper and lower layers are electrically insulated from each other.

Another problem has been detected as a result of the studies performedby the inventor of the present invention in that the resin in theperiphery of the opening is raised excessively and, thus, the via holeis disconnected.

A still further object of the present invention is to obtain amultilayered printed circuit board having furthermore improvedreliability in the connection in the via hole portion.

On the other hand, a multilayer forming technique which employsso-called RCC (RESIN COATED COPPER: Copper film having resin) as thebuilt-up multilayered printed circuit board has been suggested. Theforegoing technique has the steps of laminating RCC on a circuitsubstrate; etching the copper foil to form a through hole in a portionin which the via hole will be formed; irradiating the resin layer in thethrough hole portion with a laser beam to remove the resin layer openingas to form an opening; and filling the opening with plating so that thevia hole is formed.

Another technique has been developed as disclosed in Japanese PatentLaid-Open No. 9-36551 with which one-side circuit substrates each havinga through hole filled with a conductive substance are laminated throughadhesive layers so that a multilayered structure is formed.

The foregoing multilayered printed circuit board is subjected to aprocess for coarsening the surface of the lower conductive circuit tomaintain the adhesiveness between the surface of the lower conductivecircuit and the interlayer insulating resin layer.

The coarsening method is exemplified by a method (hereinafter called a“Cu—Ni—P plating method”) of covering and coarsening the surface of theconductive circuit with a needle shape or porous plating layer made of aCu—Ni—P alloy; a coarsening method (hereinafter called a “blackening andreducing method”) with which the surface of the conductive circuit isblackened (oxidized) and reduced; a coarsening method (hereinaftercalled a “soft etching method”) which uses mixed solution of peroxideand sulfuric acid to soft-etch the surface of the conductive circuit;and a coarsening method (hereinafter called a “scratching method”) withwhich the surface of the conductive circuit is scratched with asandpaper or the like.

However, if the conductive circuit is coarsened by the Cu—Ni—P platingmethod of the blackening and reducing method, followed by forming aninterlayer insulating resin layer, and followed by applying a laser beamto form an opening for forming the via hole in the interlayer insulatingresin layer, the coarsened surface of the conductive circuit isundesirably removed and flattened owing to the irradiation with thelaser beam. Thus, there arises a problem in that the adhesiveness withthe via hole formed above the coarsened surface becomes defective.

The reason for this lies in that the coarsened surface formed by theabove-mentioned process is colored and, thus, the colored surfaceundesirably absorbs the laser beam.

When the coarsened surface has been provided for the conductive circuitby the soft etching method or the scratching method, the coarsenedsurface does not absorb the laser beam. Since the coarsened surface hasnot sufficiently been coarsened, there arises a problem in thatsatisfactory adhesiveness cannot be realized between the conductivecircuit and the interlayer insulating resin layer.

To solve the above-mentioned problems experienced with the conventionaltechnique, a still further object of the present invention is to providea multilayered printed circuit board and a manufacturing method each ofwhich is able to realize satisfactory adhesiveness with the interlayerinsulating resin layer which is formed on the conductive circuit, withwhich flattening of the coarsened surface of the surface of theconductive circuit can be prevented when a laser beam is applied to formthe via hole in the interlayer insulating resin layer and which has avia hole (conductive circuit) having satisfactory adhesiveness.

With the conventional technique, the via hole is formed by drilling athrough hole in the interlayer insulating resin layer and by disposing ametal film in the through hole. Hitherto, the through hole has beenformed by employing photosensitive resin to constitute the interlayerinsulating resin layer and by exposing a position corresponding to thethrough hole through a mask on which a black circle has been drawn tosensitize the interlayer insulating resin layer so as to dissolve thenon-sensitized portion corresponding to the position of the blackcircle.

The foregoing photolithography method, however, encounters a limitationof the smallest diameter of the through hole, the limitation being adiameter of about 80 μm. Therefore, the foregoing method cannot meet arequirement for raising the density of the multilayered printed circuitboard. Therefore, the inventor of the present invention has come up withan idea that the through hole is formed by using a laser beam andperformed experiments. As a result, a through hole having a diameter notlarger than 80 μm can be formed.

However, a fact has been detected that the reliability of the via holeis unsatisfactory when the via hole has been formed by using the throughhole having a diameter not larger than 80 μm. The cause of the foregoingfact has been studied, thus resulting in a problem of insufficientadhesiveness between the through hole and the electroless copper platedfilm. That is, the via hole is formed by depositing the electrolesscopper plated film. Satisfactory adhesiveness cannot be realized betweenthe through hole formed by using a laser beam and having a smalldiameter and the electroless copper plated film. As a result, separationof the electroless copper plated film from the through hole causesdisconnection to occur.

On the other hand, the conventional photolithography technique has beenperformed such that the through hole is formed by performing exposureand development. Therefore, only photosensitive materials are permittedto be used. Hence it follows that the performance required for themultilayered printed circuit board cannot sometimes be satisfied.

The conventional multilayered printed circuit board suffers fromunsatisfactory reliability of solder bumps. The cause has been studied,thus resulting in the insufficient adhesiveness between the through holeand the metal film. That is, the solder bump is formed by enclosingsolder in a portion on a nickel plated film deposited on the surface ofthe conductive circuit below the opening. The adhesiveness between theconductive circuit and the nickel plated film has been unsatisfactory,causing the nickel plated film to be separated. It leads to a fact thatdisconnection of the solder bump occurs.

To solve the above-mentioned problems, a still further object of thepresent invention is to provide a multilayered printed circuit board anda manufacturing method therefor each of which is capable of forming avia hole exhibiting satisfactory reliability and having a smalldiameter.

To solve the above-mentioned problems, a still further object of thepresent invention is to provide a multilayered printed circuit board anda manufacturing method therefor each of which permits selection ofhigh-performance material for the solder resist.

A still further object of the present invention is to provide amultilayered printed circuit board and a manufacturing method thereforeach of which is capable of forming a reliable solder bump.

On the other hand, the through hole provided for a core substrate mustprecisely be formed. Thus, a through hole having a diameter smaller than100 μm cannot easily be formed by drilling. Therefore, the through holeis formed in a copper-plated laminated board by using a laser beam.

An optimum laser beam is a carbon dioxide laser because of a low costfrom the viewpoint of industrial production. However, the carbon dioxidelaser is undesirably reflected by the surface of the copper foil.Therefore, it is technical common sense that the through hole cannot beformed directly in the copper-plated laminated board by the lasermachining. Thus, a technique has been disclosed in Japanese PatentLaid-Open No. S61-99596 with which the surface of the copper foil of thecopper-plated laminated board is subjected to a blackening process (anoxidizing process), followed by applying a laser beam.

The foregoing technique, however, requires the blackening process to beperformed first, causing a problem to arise in that a long manufacturingprocess is required.

As a result of energetic studies performed by the inventors of thepresent invention, an unexpected fact has been found that reduction inthe thickness of the copper foil enables an opening to be formed in thecopper foil in spite of the reflection by the surface.

To solve the above-mentioned problems, a still further object of thepresent invention is to realize a technique which is capable of directlyforming an opening in a copper-plated laminated board and provide asubstrate having the through hole formed by the foregoing method and amultilayered printed circuit board.

Since a high density and multilayered structure has been required inrecent years, a built-up multilayered printed circuit board hasattracted attention. The multilayered circuit board is a multilayeredcircuit board having a core substrate on which conductive circuits andinterlayer insulating resin layers are alternately formed. Theconductive circuits in the layers are connected to one another through avia hole.

As the core substrate of the foregoing built-up multilayered printedcircuit board, a glass epoxy resin substrate of FR-4 grade has beenemployed.

However, the glass epoxy resin substrate of the FR-4 grade encounters aproblem in that the insulation resistance between the through holes isreduced in a HAST test and a steam test. Another problem arises in thatthe resistance of the through hole chain was excessively changed as aresult of the heat cycle test. That is, the reliability realized afteruse for a long time has been unsatisfactory.

To solve the above-mentioned problem, a core substrate which employs BT(Bis maleimide-Triazine) resin has been suggested. The foregoingsubstrate is, however, a costly substrate.

Inventors of the present invention have considered probability ofpreventing reduction in the insulation resistance between the throughholes and change in the resistance of the conductive circuit forconnecting the through holes to each other by using low-cost resin suchas epoxy resin in place of the costly resin, such as the BT resin. As aresult, an unexpected fact was found that the foregoing problem iscaused from the Tg point of the resin.

According to the present invention, a low-cost multilayered printedcircuit board is suggested which is free from reduction in theinsulation resistance between through holes as a result of the HAST testand the steam test and change in the resistance of the conductivecircuit for connecting the through holes to each other as a result of aheat cycle test.

The method of manufacturing the printed circuit board is broadly dividedinto a subtractive method (a Subtractive Process) and an additive method(an Additive Process). The subtractive method is also called an etchingmethod which is characterized by chemically corroding the surface copperfoil of a copper-plated laminated board. A method of manufacturing aprinted circuit board (a double-side board) by the subtractive processwill now briefly be described.

Initially, a copper-plated laminated board is prepared whichincorporates an insulating substrate having two sides each of which iscoated with copper foil having tens of μm. Then, an opening for forminga through hole is formed at a predetermined position of thecopper-plated laminated board by drilling or the like. If a drillingstep is performed, smears occurs in the opening for forming the throughhole, desmear solution is used to process the copper-plated laminatedboard to dissolve and remove the smears. After the desmear process hasbeen completed, electroless copper plating of the overall ground layerconstituted by copper foil and the inner surface of an opening forforming the through hole is performed so that a thin plated layer isformed. After the foregoing plating process has been completed, a maskis formed on the thin plated layer. Then, thick plated layers are formedin the portions exposed through openings of the mask by electrolyticcopper plating. After the foregoing plating process has been completed,the mask is separated. Then, etching is performed in a state in which anetching resist has been formed on the thick plated layer by solderplating or the like. The etching process is so performed as to removethe thin plated layer and the ground layer so as to divide theconductive pattern. Finally, the etching resist is separated so that arequired printed circuit board is manufactured.

The foregoing method, however, is impossible to accurately form a finepattern having a satisfactory shape. The characteristics of the etchingcauses a so-called divergent conductive pattern having a bottom which islonger than the top to easily be formed. Therefore, a pattern cannoteasily be formed in a portion (for example, a bonding pad portion) whichmust have a fine and precise structure.

In view of the foregoing, a still further object of the presentinvention is to provide a method of manufacturing a printed circuitboard with which a fine conductive pattern having a satisfactory shapecan be formed.

SUMMARY OF THE INVENTION

A method of manufacturing a multilayered printed circuit board accordingto claim 1 comprising the steps (1) to (5):

(1) pressing resin to form an interlayer insulating resin layer having ametal film formed thereon against a substrate for forming a conductorcircuit;

(2) reducing the thickness of a whole surface of the metal film byetching;

(3) forming an opening in the metal film so as to expose the interlayerinsulating resin layer;

(4) applying a laser beam from the formed opening of the metal film sideto remove the resin forming the interlayer insulating resin layerexposed through the opening so as to provide an opening for a via hole;and

(5) depositing a plating conductor in the formed opening to form the viahole.

The present invention according to claim 1 employs a metal film thinnedby etching and thus having a lowered thermal conductivity as a conformalmask. Therefore, an opening can be formed by a small output laser. Henceit follows that generation of undercut of resin for forming aninterlayer insulating resin layer can be prevented.

A method of manufacturing a multilayered printed circuit board accordingto claim 2 comprising the steps (1) to (8):

(1) pressing resin to form an interlayer insulating resin layer having ametal film formed thereon against a substrate forming a conductorcircuit;

(2) reducing the thickness of a whole surface of the metal film byetching;

(3) forming an opening in the metal film so as to expose the interlayerinsulating resin layer;

(4) applying a laser beam from the formed opening of the metal film sideto remove the resin forming the interlayer insulating resin layerexposed through the opening to provide an opening for a via hole;

(5) forming an electroless plated film on the substrate forming theconductor circuit;

(6) forming a plating resist on the substrate forming the conductorcircuit;

(7) electrolytic-plating a portion in which the plating resist is notformed; and

(8) removing the plating resist to remove the metal film and theelectroless plated film below the plating resist by etching to form thevia hole and the conductor circuit.

The present invention according to claim 2 employs a metal film thinnedby etching and thus having a lowered thermal conductivity as a conformalmask. Therefore, an opening can be formed by a small output laser. Henceit follows that generation of undercut of resin for forming aninterlayer insulating resin layer can be prevented.

After an opening for forming a via hole has been formed, an electrolesscopper plated film is formed on the metal film. Then, an electrolyticcopper plated film is formed on the electroless copper plated film. Whenthe conductive circuit and the via hole are formed, the electrolesscopper plated film lower than the resist layer is removed by etching.Since the metal film and the electroless copper plated film, which arethin films, can easily be removed, the electrolytic copper plated filmconstituting the conductive circuit and the via hole is not corrodedduring the etching process. As a result, a circuit having a fine pitchand a via hole having a precise diameter can be formed.

The present invention in claim 3 according to claim 1 or 2, the metalfilm is copper foil.

The present invention in claim 4 according to claim 1 or 2, thethickness of the metal film is made to be 5 μm to 0.5 μm in the step forreducing the thickness of the metal film by performing etching.

In accordance with claim 4, the thickness of the metal film is made tobe 5 μm to 0.5 μm. The reason for this lies in that undercut occurs ifthe thickness of the metal film is larger than 5 μm. If the thickness isnot larger than 0.5 μm, the function of the conformal mask cannot beobtained.

In accordance with claim 5, an interlayer insulating resin layerincorporating a metal film having a thickness of 5 μm to 0.5 μm ispressed against a substrate having a conductive circuit formed thereon.

In the present invention, the resin film having a metal film formedpreviously is pressed. Therefore, satisfactory flexibility can berealized which permits the resin film to easily be pressed against thesubstrate having the conductive circuit formed thereon.

According to the present invention, a method of manufacturing amultilayered printed circuit board is provided, incorporating asubstrate on which a lower conductive circuit is formed, an insulatingresin layer and an upper conductive circuit formed on the lowerconductive circuit and having a structure that the lower conductivecircuit and the upper conductive circuit are connected to each otherthrough a via hole, the method of manufacturing a multilayered printedcircuit board comprising the steps of: forming the lower conductivecircuit on the substrate; forming the insulating resin layer on thelower conductive circuit; forming a coarsened surface on the surface ofthe insulating resin layer; forming, on the coarsened surface, a metallayer having an opening through which a portion of the coarsened surfaceis exposed; irradiating the coarsened surface exposed through theopening with a laser beam to remove the insulating resin layer to forman opening for the via hole; and forming the upper conductive circuitand the via hole.

According to the present invention, a method of manufacturing amultilayered printed circuit board is provided, incorporating asubstrate on which a lower conductive circuit is formed, an insulatingresin layer and an upper conductive circuit formed on the lowerconductive circuit and having a structure that the lower conductivecircuit and the upper conductive circuit are connected to each otherthrough a via hole, the method of manufacturing a multilayered printedcircuit board comprising the steps of: forming the lower conductivecircuit on the substrate; laminating, heating and compressing metal foilhaving a coarsened surface formed either surface thereof and theinsulating resin layer formed on the coarsened surface such that theinsulating resin layer makes contact with the lower conductive circuitso that the metal foil is integrated; etching a portion of the metalfoil to form an opening to expose the coarsened surface of theinsulating resin layer; irradiating the coarsened surface exposedthrough the opening with a laser beam to remove the insulating resinlayer so as to form an opening for forming the via hole; and forming theupper conductive circuit and the via hole.

As a result of energetic studies performed by the inventors of thepresent invention, a fact has been found that the cause of residuesproduced in the operation for forming the opening for forming the viahole is the structure that the surface which is irradiated with thelaser beam is a mirror surface which reflects the laser beam to inhibitcomplete removal of the insulating resin layer.

The present invention uses the detected fact such that the surfaceirradiated with the laser beam is formed into the coarsened surface toprevent reflection of the laser beam.

In the present invention, the resist against the laser beam is metallayer or metal foil. Moreover, the opening is formed in the metal layeror the metal foil. The opening is irradiated with a laser beam capableof realizing a diameter of a spot light which is larger than thediameter of the opening so that the opening for forming the via hole isformed in the insulating resin layer.

In the present invention, the surface of the insulating resin layerexposed through the opening in the metal layer or the like is formedinto the coarsened surface. Therefore, reflection of the laser beam canbe prevented and the insulating resin layer can completely be removed.Since upward expansion of the periphery of the insulating resin layercan be prevented, also disconnection of the via hole can be prevented.

Although the reason why the expansion can be prevented cannot clearly bedetected, an estimation can be made that the coarsened surface has ahigh absorption with respect to a laser beam and the resin is easilyformed into plasma.

The inventors of the present invention have energetically studied inorder to realize the foregoing object. As a result, etching solutioncontaining a cupric complex and organic acid is used to etch theconductive circuit. Thus, flattening can be prevented when the surfaceof the conductive circuit is irradiated with a laser beam. Moreover, acoarsened surface exhibiting satisfactory adhesiveness with theinterlayer insulating resin layer formed on the conductive circuit andthe via hole can be formed. The foregoing detected fact is used toestablish the present invention having the following essential portion.

A multilayered printed circuit board according to claim 12 comprising: asubstrate on which a conductive circuit is formed; an interlayerinsulating resin layer formed on the conductive circuit; an opening forforming a via hole formed in the interlayer insulating resin layer; andanother conductive circuit including a via hole and formed on theinterlayer insulating resin layer, wherein

the surface of the conductive circuit is subjected to a coarseningprocess using etching solution containing cupric complex and organicacid, and

stripe pits and projections are formed on the inner wall of the openingfor forming the via hole.

According to claim 13, a method of manufacturing a multilayered printedcircuit board including (1) a step of forming a conductive circuit; (2)a step of forming an interlayer insulating resin layer on the conductivecircuit; (3) a step of applying a laser beam to form an opening forforming a via hole in the interlayer insulating resin layer; and (4) astep of forming another conductive circuit including a via hole on theinterlayer insulating resin layer, wherein

the surface of the conductive circuit is subjected to a coarseningprocess by using etching solution containing cupric complex and organicacid.

It is preferable that the method of manufacturing the multilayeredprinted circuit board has the step of spraying etching solutioncontaining the cupric complex and the organic acid to the surface of theconductive circuit or the conductive circuit is immersed in the etchingsolution under a bubbling condition so that the surface of theconductive circuit is subjected to the coarsening process.

In claim 15, a multilayered printed circuit board incorporatinginterlayer insulating resin layers and conductive layers laminatedalternately and structured such that the conductive layers are connectedto one another through via holes each of which is formed by forming ametal film in a through hole formed in each of the interlayer insulatingresin layers, said multilayered printed circuit board according to thepresent invention comprising:

stripe pits and projections formed on the side wall of the through hole.

An aspect of the present invention according to claim 15 has thestructure that stripe pits and projections are provided for the sidewall of the through hole. Thus, the area of connection with the metalfilm can be enlarged, causing the adhesiveness to be improved. Thus, areliable via hole can be formed.

Since the stripe pits and projections are formed in the direction of theopening, separation of the via hole can be prevented if force is exertedin the vertical direction of the via hole. Therefore, if the resin isleft in the through hole for forming the via hole and the residue isexpanded owing to heat to upwards move the via hole, separation can beprevented and reliability can be maintained in the connection.

The bump is provided for the via hole. If an element, such as an ICchip, having a different coefficiency of thermal expansion is mounted,force is exerted in the vertical direction of the via hole owing to theheat cycle. Also in the foregoing case, the stripe pits and projectionsin the direction of the opening prevent separation of the via hole.

It is preferable that the stripe pits and projections have the structurethat the intervals between projections (or pits) are 1 μm to 20 μm. Ifthe interval is too long or too short, the adhesiveness effect with themetal film deteriorates. The foregoing interval is substantially thesame as ½ of the wavelength of the laser beam.

It is preferable that the metal film for forming the via hole is formedsuch that the electroless copper plated film and the electrolytic copperplated film are formed in this order from a position adjacent to theside wall of the through hole. The electroless copper plated film isharder than the electrolytic copper plated film. Moreover, the stripepits and projections are formed into a pseudo coarsened surface.Therefore, if separating force is exerted, breakage of the metal filmdoes not cause the via hole to be separated from the through hole.

It is most preferable that a coarsened surface having an average surfaceroughness Ra of about 0.05 μm to about 5 μm is formed (FIG. 31 (A) whichis an enlarged view) on the surface of the stripe pits and projections.The reason for this lies in that the adhesiveness can furthermore beimproved.

When the coarsened surface of the side wall of the through hole iscomplicated, transmission of a high-frequency signal causes delay intransmission to occur and noise to be produced owing to the skin effect.The stripe pits and projections according to the present invention areformed at the intervals of 1 μm to 20 μm. Therefore, the skin effectdoes not raise a critical problem. Moreover, the adhesiveness can beimproved.

It is most preferable that the surface of the conductive circuit towhich the through hole reaches is made of an electrolytic copper platedfilm. The electrolytic copper plated film has small crystal particles ascompared with those of the electroless copper plated film. Moreover, theelectrolytic copper plated film exhibits excellent glossiness to easilyreflect a laser beam. Therefore, the electrolytic copper plated film isan optimum film in a case where incident light of the laser beam andreflected light are caused to interfere with each other as describedlater.

It is preferable that the surface of the conductive circuit to which thethrough hole reaches has a metal coarsened layer.

When the metal coarsened layer is formed on the surface of theconductive circuit, the laser beam is reflected by the surface of themetal coarsened layer to enable the laser beam to be reflected by thesurface of the metal coarsened layer to cause the incident light of thelaser beam and the reflected wave to interfere with each other. Thus,the stripe pits and projections formed in the direction of the openingcan be provided for the surface of the wall of the through hole of theinterlayer insulating resin layer.

Since the coarsened layer enables the reflection of the laser beam to beprevented to a level not higher than a predetermined level, residualresin on the surface of the conductive circuit can be prevented. Sincethe coarsened layer enables the adhesiveness with the interlayerinsulating resin layer to be maintained, separation of the interlayerinsulating resin layer owing to deterioration in the thermal shock ofthe laser beam can be prevented.

When the coarsened layer is not provided, the reflection is raisedexcessively, causing residue of the resin to easily occur. If anoxidizing (a blackening) process is performed to form the coarsenedlayer, the laser beam is undesirably absorbed. Thus, the laser beamcannot be reflected.

It is preferable that Rj of the coarsened layer is 0.05 μm to 20 μm. IfRj is 0.05 μm or smaller, the reverse side is blackened. Thus, the laserbeam is undesirably absorbed. If Rj is larger than 20 μm, the laser beamscatters. In either of the two cases, incident light a reflected wavecannot cause to interfere with each other.

It is preferable that the coarsened layer is a coarsened layer obtainedby non-acidic chemical coarsening process, such as physical coarseningincluding a polishing process, an oxidizing (a blackening) and reducingprocess, a process using sulfuric acid and hydrogen peroxide solution ora coarsening process using etching solution composed of cupric complexand organic acid under coexistence of oxygen. As an alternative to this,it is preferable that the coarsened layer is a coarsened layerobtainable from a plating process using an alloy, such as Cu—Ni—P orCu—Co—P. The reason for this lies in that the foregoing coarsened layeris able to reflect the laser beam.

Plating of Cu—Ni—P may be performed by using electroless plating bath,the pH of which is 9 and which is water solution of, for example,coppersulfate (0.1×10⁻² to 25×10⁻² mol/l), nickel sulfate (0.1×10⁻³ to40×10⁻³ mol/l), citric acid (1×10⁻² to 20×10⁻² mol/l), sodiumhypophosphite (1×10⁻¹ to 10×10⁻¹ mol/l), boric acid (1×10⁻¹ to 10.0×10⁻¹mol/l) or a surface active agent (Surfinol 465 manufactured by NissinChemical Industry) (0.1 g/l to 10 g/l).

It is preferable that the cupric complex according to the presentinvention is a cupric complex of azole. The cupric complex of azole isemployed as an oxidizer for oxidizing metal copper. The azole may bediazole, triazole or tetra azole. Among the foregoing materials, it ispreferable that any one of the following material is employed:imidazole, 2-methyl imidazole, 2-ethyl imidazole, 2-ethyl-4-methylimidazole, 2-phenyl imidazole or 2-undecyl imidazole. It is preferablethat the quantity of cupric complex of azole which must be added is 1 wt% to 15 wt %. The reason for this lies in that noble metal, such as Pd,exhibiting satisfactory solubility, stability and constituting crystalcore can be dissolved.

To dissolve copper oxide, organic acid is mixed with the cupric complexof azole.

Specifically, it is preferable that the organic acid is at least onetype of material selected from a group consisting of formic acid, aceticacid, propionic acid, butyric acid, valerianic acid, capronic acid,acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid,glutaric acid, maleic acid, benzoic acid, glycollic acid, lactic acid,malic acid and sulfamic acid. It is preferable that the content of theorganic acid is 0.1 wt % to 30 wt % to maintain the solubility ofoxidized copper and dissolution stability.

The produced cuprous complex is dissolved owing to an action of the acidso as to be combined with oxygen so that cupric complex is producedwhich is again contributed to the oxidation of copper.

To assist the dissolution of copper and oxidation of azole, halogenions, for example, fluorine ions, chlorine ions or bromine ions, may beadded to the etching solution. In the present invention, hydrochloricacid or sodium chloride may be added to supply halogen ions. It ispreferable that the quantity of halogen ions is 0.01 wt % to 20 wt % toimprove the adhesiveness between the formed coarsened surface and theinterlayer insulating resin layer.

The cupric complex of azole and the organic acid (and halogen ions ifnecessary) are dissolved in water to adjust the etching solution.

The oxidizing and reducing process may be performed by using anoxidizing bath of 1 g/l to 100 g/l NaOH, 1 g/l to 100 g/l NaClO₂ and 1g/l to 50 g/l Na₃PO₄ and a reducing bath of 1 g/l to 100 g/l NaOH to 1g/l to 50 g/l NaBH₄.

The metal coarsened layer may be coated with at least one type of metalmaterials selected from a group consisting of Ti, Al, Cr, Zn, Fe, In,Tl, Co, Ni, Sn, Pb, Bi and noble metal to maintain glossiness andimprove adhesiveness with the solder resist. It is preferable that thethickness of the selected metal material is 0.01 μm to 10 μm.

In the present invention, it is preferable that the diameter of thethrough hole for forming the via hole is 80 μm or smaller. The foregoingprecise via hole has a small area of contact between the metal film forforming the via hole and the side wall of the through hole for formingthe via hole. Therefore, separation considerably easily occurs.Therefore, the formation of the conventional coarsened surface cannotsatisfactorily prevent the separation. If the coarsened surface is madeto be excessively complicated, the foregoing skin effect problem ofdelay in transmission and production of noise arises. The presentinvention is able to overcome the foregoing problems.

The present invention in claim 16 according to claim 15, the interlayerinsulating resin layer is made of thermosetting resin or a compositematerial of the thermosetting resin and thermoplastic resin.

An aspect of the present invention according to claim 16 has a structurethat the interlayer insulating resin layer is made of thermosettingresin or a composite material of thermosetting resin and thermoplasticresin. Therefore, stripe pits and projections can easily be formed owingto interference of the laser beam. Note that only the thermosettingresin, which encounters dissolution of resin, cannot form clear stripepits and projections.

The present invention in claim 17 according to claim 15, the interlayerinsulating resin layer contains acrylic monomer.

It is preferable that an aspect of the present invention according toclaim 17 is structured such that the interlayer insulating resin layercontains acrylic monomer. The reason for this lies in that residues ofthe resin can be reduced.

The acrylic monomer crosslinks monomer or oligomer of the thermosettingresin (including the thermosetting resin, a portion of which has beensensitized).

The acrylic monomer can be decomposed relatively easily. Therefore, theacrylic monomer is contained in the molecular chain, the acrylic monomeris decomposed owing to a laser beam, causing the thermosetting resin tohave low molecular weight. Moreover, the resin having the low molecularweight is decomposed by the laser beam. Therefore, formation into plasmacan easily be formed, causing residue of resin to substantially beeliminated.

The acrylic monomer may be any one of a variety of commercial products.For example, DPE-6A KAYAMAER PM-2 or PM-21 manufactured by Nihon Kayaku,R-604 manufactured by Kyoei or Aronix M-315, M-325 or M-215 manufacturedby Toa may be employed.

DPE-6A is expressed by chemical formula 1 shown in FIG. 59, R-604 isexpressed by chemical formula 2, Aronix M-315 is expressed by chemicalformula 3, M215 is expressed by chemical formula 4 shown in FIG. 60 andKAYAMAER PM-2 and PM-21 is expressed by chemical formula 5.

A method of manufacturing a multilayered printed circuit board accordingto claim 18 comprising at least the steps (a) to (d):

(a) forming a conductive circuit;

(b) coating the conductive circuit with resin;

(c) irradiating the resin with a carbon-dioxide gas laser beam to form athrough hole which reaches the conductive circuit such that thecarbon-dioxide gas laser beam is vertically applied to the conductivecircuit below the resin to cause interference of reflected wave from theconductive circuit and incident wave to occur so that stripe pits andprojections are formed on the side wall of the through hole; and

(d) coating the through hole with metal to form a via hole.

In claim 18, an aspect has a structure that the conductive circuit belowthe resin is vertically irradiated with a carbon-dioxide-gas laser beamto cause interference between reflected wave from the conductive circuitand incident wave to occur. Therefore, the stripe pits and projectionscan be formed on the side wall of the through hole. Therefore, theadhesiveness with metal can be improved so that a reliable via hole canbe formed.

The present invention in claim 19 according to claim 18, the resin isthermosetting resin or a composite material of the thermosetting resinand thermoplastic resin.

An aspect of claim 19 has a structure that the interlayer insulatingresin layer is made of the thermosetting resin or a composite of thethermosetting resin and thermoplastic resin. Therefore, the stripe pitsand projections can easily be formed by the laser beam.

The present invention in claim 20 according to claim 18, the step offorming the via hole includes a step of forming a resist after anelectroless copper plated film has been formed in the through hole andsupplying electric power through the electroless plated film to form anelectrolytic plated film in a portion in which the resist is not formed.

An aspect of claim 20 has a structure that an electroless copper platedfilm is formed on the surface of the through hole, followed by forming aresist. Then, electric power is supplied through the electroless copperplated film to form an electrolytic copper plated film in a portion inwhich no resist is formed. Thus, the via hole is formed. Since thestripe pits and projections are formed on the side wall of the throughhole by using the interference of the laser beam and then theelectroless plated film is formed, the adhesiveness between theelectroless copper plated film and the through hole in the interlayerinsulating resin layer can be improved. As a result, a reliable via holecan be formed.

The present invention in claim 21 according to claim 18, the interlayerinsulating resin layer contains acrylic monomer.

A method of manufacturing a printed circuit board according to claim 22comprising at least the steps (a) and (b):

(a) forming a solder-resist layer on the surface of a substrate on whicha conductive circuit has been formed; and

(b) irradiating the solder-resist layer with a laser beam to form athrough hole which reaches the conductive circuit.

An aspect claim 22 has a structure that the through hole is formed inthe solder resist layer by using the laser beam. Therefore, the materialis not limited to the photosensitive material. As a material of thesolder-resist layer, any one a variety of materials may be employed.

Moreover, defective conduction owing to residue of the solder-resistresin can be prevented.

It is most preferable that the surface of the conductive circuit isconstituted by the electrolytic plated film. The electrolytic platedfilm has large crystal particles as compared with those of theelectroless plated film. Moreover, the electrolytic plated film exhibitsexcellent glossiness to easily reflect a laser beam. Therefore, theelectrolytic plated film is an optimum film in a case where incidentlight of the laser beam and reflected light are caused to interfere witheach other as described later.

The present invention in claim 23 according to claim 22, the surface ofthe conductive circuit has a metal coarsened layer.

An aspect of claim 23 is characterized in that the surface of theconductive circuit has a metal coarsened layer.

Since the metal coarsened layer is formed on the surface of theconductive circuit, the laser beam can be reflected by the surface ofthe metal coarsened layer. Thus, as described later, incident waves ofthe laser beam and reflected waves can be caused to interfere with eachother. Thus, the stripe pits and projections formed in the direction ofthe opening can be provided for the wall of the through hole of thesolder-resist layer.

The present invention in claim 24 according to claim 22, (c) a step offorming a bump made metal having a low melting point in the through holeis performed after the step (b).

An aspect claim 24 has a structure that a bump made of alow-melting-point metal is provided for the through hole in thesolder-resist layer. Thus, an electrode of an IC chip can be connectedto the foregoing bump or the foregoing bump may be used to mount theprinted circuit board to another printed circuit board.

The present invention in claim 25 according to claim 22, a laser beam ina single mode is applied in the step of forming the through hole so thata through hole having a diameter of 300 μm to 650 μm is formed.

An aspect of claim 25 has a structure that a single-mode laser beam, thediameter of a spot light of which can be enlarged is applied. Therefore,a through hole for forming a through hole having a diameter of 300 μm to650 μm, that is, a through hole for forming a bump for establishing theconnection with another printed circuit board (for example, a motherboard) can be formed in the solder-resist layer.

The present invention in claim 26 according to claim 22, a laser beam ina multi mode is applied in the step of forming the through hole so thata through hole having a diameter of 50 μm to 300 μm is formed.

An aspect of claim 26 has a structure that a multimode laser beam, thediameter of which can be reduced is applied. Therefore, a through holefor forming a through hole having a diameter of 50 μm to 300 μm, thatis, a through hole for forming a bump for establishing the connectionwith an IC chip can be formed in the solder-resist layer.

The present invention in claim 27 according to any of claims 22 to 26,the step of forming the through hole is performed such that thecarbon-dioxide gas laser beam is vertically applied to the conductivecircuit below the resin to cause interference of reflected wave from theconductive circuit and incident wave to occur so that stripe pits andprojections are formed on the side wall of the through hole.

An aspect claim 27 has a structure that a step for forming the throughhole is arranged such that reflected wave of the carbon-dioxide gaslaser beam and the incident wave are caused to interfere with eachother. Thus, the stripe pits and projections are formed on the side wallof the through hole. Therefore, when the metal film is provided for thethrough hole, the metal film can be brought into hermetic contact withthe through hole.

The present invention in claim 28 according to claim 27, the step offorming the bump is performed such that a metal film is provided for thethrough hole having the side wall provided with the stripe pits andprojections, and then metal having a low melting point is enclosed.

An aspect of claim 28 has a structure that the metal film is providedfor the through hole having the side wall. Then, low-melting-point metalis enclosed to form the bump. The metal film is brought into hermeticcontact with the through hole having the stripe pits and projections sothat the bump is strongly connected to the conductive circuit.

In claim 29, a printed circuit board incorporating a substrate providedwith a conductive circuit and having a surface on which a solder-resistlayer is formed, said printed circuit board according to the presentinvention comprising:

stripe pits and projections formed on the side wall of a through holeformed in the solder-resist layer.

An aspect of claim 29 has a structure that the stripe pits andprojections are formed on the side wall of the through hole formed inthe solder-resist layer. Therefore, when the metal film is formed on thesurface of the through hole, the metal film can strongly be brought intohermetic contact with the through hole.

A heat cycle sometimes causes a crack to sometimes occur in thesolder-resist layer owing to the difference between the coefficiency ofthermal expansion of the metal film and that of the solder-resist layer.However, the present invention causes the metal film and the wall of thethrough hole of the solder-resist layer to be brought into hermeticcontact to each other. Therefore, a crack cannot easily be formed.

Since the stripe pits and projections are provided for the wall of thethrough hole in the direction of the opening, the contact between thewall and the low-melting-point metal is made to be line contact in placeof the plane contact. Therefore, a phenomenon (migration) that thelow-melting-point metal is ionized and diffused under hot and highhumidity conditions can be prevented. The employed low-melting-pointmetal and the metal film are the same as those described above. It ismost preferable that the surface of the conductive circuit isconstituted by an electolytically plated film. The electolyticallyplated film has smaller crystal particles as compared with theelectroless platted film and exhibiting excellent glossiness. Moreover,discoloration, called “color change owing to plating” can be prevented.Thus, the laser beam can easily be reflected. Thus, the stripe pits andprojections can be formed on the surface of the wall in the direction ofthe opening.

It is preferable that the stripe pits and projections have the structurethat the intervals between projections (or pits) are 1 μm to 20 μm. Ifthe interval is too long or too short, the adhesiveness effect with themetal film deteriorates. A similar state is realized to that realized bythe plane contact and, therefore, the foregoing effect cannot beobtained. The foregoing interval is substantially the same as ½ of thewavelength of the laser beam.

The low-melting-point metal may be solder, such as Sn/Pb, Ag/Sn orAg/Sn/Cu. The foregoing bump can be formed through a metal filmmade ofNi/Au, Ni/Pd/Au, Cu/Ni/Au or Cu/Ni/Pd/Au. Adjustments are performed suchthat the thickness of the Cu layer and that of the Ni layer is 0.1 μm to10 μm and that of each of the Pd layer and the Au layer is 0.01 μm to 10μm.

The present invention in claim 30 according to claim 29, a bump made ofmetal having a low melting point is formed in the through hole through ametal film.

An aspect of claim 30 has a structure that the low-melting-point metalis enclosed to form the bump. When the metal film is brought intohermetic contact with the through hole having the stripe pits andprojections, the bump can strongly be connected to the conductivecircuit.

The present invention in claim 31 according to claim 29 or 30, thesolder-resist layer is made of thermosetting resin or a compositematerial of the thermosetting resin and thermoplastic resin.

An aspect of claim 31 has a structure that the solder-resist layer isconstituted by thermosetting resin or a composite of the thermosettingresin and the thermoplastic resin. Therefore, the stripe pits andprojections can easily be formed on the side surface of the through holeby the laser beam. When only the thermoplastic resin is employed, theresin is undesirably dissolved. Thus, clear pits and projections cannotbe formed.

The present invention in claim 32 according to any of claims 29 to 31, acoarsened layer is formed on the surface of the conductive circuit.

An aspect of claim 32 is characterized in that the surface of theconductive circuit has a metal coarsened layer.

Since the metal coarsened layer is formed on the surface of theconductive circuit, the laser beam can be reflected by the surface ofthe metal coarsened layer. Thus, the incident wave and the reflectedwave of the laser beam can be caused to interfere with each other. Thus,the stripe pits and projections can be formed on the surface of the wallof the through hole in the solder-resist layer in the direction of theopening.

In the present invention, it is desirable to use an adhesive forelectroless plating as the above interlayer resin insulating layer. Inthis adhesive for electroless plating, it is optimal that heat resistingresin particles soluble to a hardened acid or oxidizing agent aredispersed into unhardened heat resisting resin difficult to be solubleto an acid or an oxidizing agent.

The heat resisting resin particles are dissolved and removed byprocessing these resin particles using an acid or an oxidizing agent anda coarsened face constructed by an anchor formed in the shape of anoctopus trap can be formed on a layer surface.

In the above adhesive for electroless plating, the above heat resistingresin particles particularly hardened are desirably constructed by using{circle around (1)} heat resisting resin powder having an averageparticle diameter equal to or smaller than 10 μm, {circle around (2)}cohesive particles formed by aggregating heat resisting resin powderhaving an average particle diameter equal to or smaller than 2 μm,{circle around (3)} a mixture of heat resisting powder resin powderhaving an average particle diameter from 2 to 10 μm and heat resistingresin powder having an average particle diameter equal to or smallerthan 2 μm, {circle around (4)} pseudo-particles in which at least onekind of heat resisting resin powder or inorganic powder having anaverage particle diameter equal to or smaller than 2 μm is attached tothe surface of heat resisting resin powder having an average particlediameter from 2 to 10 μm, {circle around (5)} a mixture of heatresisting powder resin powder having an average particle diameter from0.1 to 0.8 μm and heat resisting resin powder having an average particlediameter greater than 0.8 μm and smaller than 2 μm, and {circle around(6)} heat resisting powder resin powder having an average particlediameter from 0.1 to 10 μm. This is because these materials can form amore complicated anchor.

A depth of the coarsened face is preferably set to secure a closeattaching property such that Rj=0.01 to 20 μm. In particular, Rjpreferably ranges from 0.1 to 5 μm in the semi-additive method since anelectroless plating film can be removed while the close attachingproperty is secured.

The heat resisting resin difficult to be soluble to an acid or anoxidizing agent mentioned above is desirably constructed by “a resincomplex constructed by thermosetting resin and thermoplastic resin”, or“a resin complex constructed by photosensitive resin and thermoplasticresin”. The former has a high heat resisting property. The latter isdesirable since the opening for the via hole can be formed byphotolithography.

The above thermosetting resin can be constructed by using epoxy resin,phenol resin, polyimide resin, etc. When the thermosetting resin isphotosensitized, a thermosetting group acrylic-reacts on methacrylicacid, acrylic acid, etc. Acrylate of the epoxy resin is particularlyoptimal.

The epoxy resin can be constructed by using epoxy resin of novolak typesuch as phenol novolak type, cresol novolak type, etc.,dicyclopentadiene-modified alicyclic epoxy resin, etc.

The thermoplastic resin can be constructed by using polyether sulfone(PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylenesulfide (PPES), polyphenyl ether (PPE), polyether imide (PI), etc.

A mixing ratio of the thermosetting resin (photosensitive resin) and thethermoplastic resin is preferably set such that thermosetting resin(photosensitive resin)/thermoplastic resin=95/5 to 50/50. This isbecause a high toughness value can be secured without reducing a heatingresisting property.

A mixing weight ratio of the above heat resisting resin particles ispreferably set to range from 5 to 50 weight % and desirably range from10 to 40 weight % with respect to the solid content of a heat resistingresin matrix.

The heat resisting resin particles are preferably constructed by aminoresin (melamine resin, urea resin, guanamine resin), epoxy resin, etc. Aacrylic-system monomer can be used.

The adhesive may be constructed by two layers having differentcompositions.

Various kinds of resins can be used as a solder resist layer added to asurface of the multilayer build-up wiring board. For example, it ispossible to use bisphenol A-type epoxy resin, acrylate of bisphenolA-type epoxy resin, novolak type epoxy resin, resin formed by hardeningacrylate of novolak type epoxy resin by an amine-system hardening agent,an imidazole hardening agent, etc.

There is a case in which such a solder resist layer is separated sincethe solder resist layer is constructed by resin having a stiff skeleton.Therefore, the separation of the solder resist layer can be alsoprevented by arranging a reinforcing layer.

The above acrylate of the novolak type epoxy resin can be constructed byusing epoxy resin in which glycidyl ether of phenol novolak and cresolnovolak reacts with acrylic acid, methacrylic acid, etc.

The above imidazole hardening agent is desirably formed in a liquidstate at 25° C. since the imidazole hardening agent can be uniformlymixed in the liquid state.

Such a liquid state imidazole hardening agent can be constructed byusing 1-benzyl-2-methylimidazole (product name: 1B2MZ),1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and4-methyl-2-ethylimidazole (product name: 2E4MZ).

An adding amount of this imidazole hardening agent is desirably set torange from 1 to 10 weight % with respect to a total solid content of theabove solder resist composition substance. This is because the imidazolehardening agent is easily uniformed and mixed if the adding amount lieswithin this range.

A composition substance prior to the hardening of the above solderresist is desirably constructed by using a solvent of a glycol ethersystem as a solvent.

In the solder resist layer using such a composition substance, no freeacid is caused and no copper pad surface is oxidized. Further, a harmfulproperty with respect to a human body is low.

Such a solvent of the glycol ether system is constructed by using thefollowing structural formula, particularly desirably using at least onekind selected from diethylene glycol dimethyl ether (DMDG) andtriethylene glycol dimethyl ether (DMTG). This is because these solventscan perfectly dissolve benzophenone and Michler's ketone as reactionstarting agents at a heating temperature from about 30 to 50° C.

CH₃O—(CH₂CH₂O)_(n)—CH₃(n=1 to 5)

This solvent of the glycol ether system preferably has 10 to 70 wt %with respect to a total weight amount of the solder resist compositionsubstance.

As explained above, various kinds of antifoaming and leveling agents,thermosetting resin for improving a heat resisting property and anantibasic property and giving a flexible property, a photosensitivemonomer for improving resolution, etc. can be further added to thesolder resist composition substance.

For example, the leveling agent is preferably constructed by monomer ofacrylic ester. A starting agent is preferably constructed by Irugacure1907 manufactured by CHIBAGAIGI. A photosensitizer is preferablyconstructed by DETX-S manufactured by NIHON KAYAKU.

Further, a coloring matter and a pigment may be added to the solderresist composition substance since a wiring pattern can be hidden. Thiscoloring matter is desirably constructed by using phthalocyaline green.

Bisphenol type epoxy resin can be used as the above thermosetting resinas an adding component. In this bisphenol type epoxy resin, there arebisphenol A-type epoxy resin and bisphenol F-type epoxy resin. Theformer is preferable when an antibasic property is seriously considered.The latter is preferable when low viscosity is required (when a coatingproperty is seriously considered).

A polyhydric acrylic-system monomer can be used as the abovephotosensitive monomer as an adding component since the polyhydricacrylic-system monomer can improve resolution. For example, DPE-6Amanufactured by NIHON KAYAKU and R-604 manufactured by KYOEISYA KAGAKUcan be used as the polyhydric acrylic-system monomer.

These solder resist composition substances preferably have 0.5 to 10Pa·s in viscosity at 25° C. and more desirably have 1 to 10 Pa·s inviscosity since these solder resist composition substances are easilycoated by a roll coater in these cases.

In claim 34, a method of manufacturing a multilayered printed circuitboard such that a through hole is formed in a double-side copper-platedlaminated board by performing a laser machining and the through hole ismade to be conductive to form a through hole so that a core substrate ismanufactured, and

an interlayer insulating resin layer and a conductive circuit are formedon the core substrate, said method of manufacturing a multilayeredprinted circuit board comprising the step of:

making the thickness of copper foil of the double-side copper-platedlaminated board to be smaller than 12 μm.

In claim 37, a substrate for forming a through hole such that a throughhole is formed in a double-side copper-plated laminated board and thethrough hole is made to be conductive so that a through hole is formed,said substrate comprising:

taper provided for the through hole.

In claim 40, a multilayered printed circuit board incorporating asubstrate in the form of a double-side copper-plated laminated board inwhich a through hole is formed such that the through hole is made to beconductive so that a through hole is formed and an interlayer insulatingresin layer and a conductive circuit are formed on at least either sideof the substrate, said multilayered printed circuit board comprising:

taper provided for the through hole.

As a result of energetic studies performed by the inventors of thepresent invention, the following fact was detected: the reason why anopening cannot be formed in copper foil having a thickness of 12 μm bythe carbon-dioxide gas laser beam is not reflection at the surface. Theforegoing fact is caused from the large thickness of the copper foilwith which thermal conduction easily occurs. Thus, the energy of thelaser beam is converted into heat which is undesirably conducted.

The thickness of the copper foil is smaller than 12 μm, preferably about1 μm to about 10 μm. Thus, conversion of the energy of the laser beaminto heat which is conducted as described above can be prevented. Thus,formation of an opening using the laser beam can be realized.

The copper-plated laminated board according to the present invention maybe a copper-plated laminated board obtained by bonding copper foil toprepreg, such as glass-cloth epoxy resin, glass-cloth bismaleimide-triazine resin or glass-cloth fluororesin.

It is preferable that the thickness of the copper foil is 1 μm to 10 μm.The reason for this lies in that an opening can easily be formed by thelaser beam if the thickness is 10 μm or smaller. If the thickness issmaller than 1 μm, blister or the like occurs.

The thickness of the copper foil is adjusted by etching. Specifically,chemical etching is employed which uses sulfuric acid and hydrogenperoxide solution, ammonium persulfate solution, cupric chloridesolution or ferric chloride solution; or physical etching, such asion-beam etching is employed.

It is preferable that the thickness of the copper-plated laminated boardis 0.5 mm to 1.0 mm. If the thickness is too large, the opening cannotbe formed. If the thickness is too small, warp or the like occurs.

It is preferable that the carbon-dioxide gas laser beam for use in thepresent invention is a short-pulse laser of 20 mJ to 40 mJ and 10⁻⁴second to 10⁻⁸ second.

The number of shots of the laser beams is 5 shots to 100 shots.

It is preferable that the diameter of the through hole which must beformed is 50 μm to 150 μm. If the thickness is smaller than 50 μm, thesurface of the wall cannot be made to be conductive by plating or thelike. If the thickness is larger than 150 μm, a drill work enables anadvantage to be realized.

If the diameter of the through hole is larger than 100 μm, the throughhole encounters taper. Taper occurs on the side on which the laser beamis made incident such that the diameter of the through hole is enlarged.

When the laser beam is applied from the right side or the reverse side,a through hole having a cross section formed into a concave shape isundesirably formed.

The foregoing through hole is made to be conductive by electric plating,electroless plating, sputtering, evaporation or enclosure of conductivepaste.

When the conductive paste is enclosed, it is preferable that taper isprovided for the through hole to easily enclose the paste.

Also in a case where the through hole is formed by metalizing thesurface of the inner wall by electric plating, electroless plating,sputtering or evaporation, the through hole can be filled with a filler.

The inner wall of the metalized through hole may be coarsened.

When the inner wall of the through hole is metalized, it is preferablethat each of the thickness of the copper foil and that of the metalizedlayer (for example, the electroless plated layer) is 10 μm to 30 μm.

The filler may be any one of a variety of materials including a fillerconstituted by inorganic particles made of bis phenol F epoxy resin,silica or alumina, metal particles and resin.

The conductive circuit is provided for the substrate having the throughhole structured as described above. The conductive circuit is formed byan etching process.

It is preferable that the surface of the conductive circuit is subjectedto a coarsening process in order to improve the adhesiveness.

Then, the interlayer insulating resin layer made of insulating resin isformed.

The insulating resin may be thermosetting resin, thermoplastic resin ortheir composite resin. In the present invention, the interlayerinsulating resin layer may be adhesive agent for electroless plating.The opening can be formed in the foregoing interlayer insulating resinlayer by a laser beam, exposure or a development process.

In claim 45, a built-up multilayered printed circuit board according tocomprising: a substrate having a through hole and a conductive circuitand structured such that interlayer insulating resin layers andconductive circuits are alternately formed and the conductive circuitsin the different layers are electrically connected to one anotherthrough via holes formed in the interlayer insulating resin layers,wherein

the substrate is a glass epoxy resin substrate made of epoxy resinhaving Tg point of 190° C. or higher.

As a result of energetic studies performed by the inventors of thepresent invention, the following fact was detected: the reason why theinsulation resistance between the through holes is reduced during theHAST test and the steam test is that metal, such as copper, which formsthe through hole is ionized and ions are moved (migration) between thethrough holes, causing the insulation resistance to be reduced.

Another fact was found that the resistance of the conductive circuitwhich connects the through holes to each other after the heat cycle testlies in that thermal expansion and contraction result in the conductivecircuit resist the plated through hole being broken.

A fact was detected that the migration and thermal expansion andcontraction can be prevented by raising the crosslinking density of theepoxy resin to raise the Tg point.

If the Tg point of the epoxy resin is not lower than 190° C., theforegoing problems can be prevented. As a result, the ionization of themetal which forms the through hole and ions are moved (migration) asdescribed above to reduce the insulation resistance between the platedthrough holes during the HAST test and the steam test can be prevented.Moreover, the thermal expansion and contraction occurring in the heatcycle test resulting in the conductive circuit or the through hole beingbroken and thus the resistance is changed, can be prevented.

Note that the epoxy resin is low-cost resin as compared with BT resin.

As the glass epoxy resin substrate having a Tg point of 190° C. orhigher (a DMA method (temperature rise rate: 2° C./minute)), a knownsubstrate developed for a mass-lamination type multilayered printedcircuit board may be used.

For example, any one of the foregoing materials may be employed: HL830(Tg point: 217° C.) or HL830FC (Tg point: 212° C.) manufactured byMitsubishi Gas Chemical, MCL-E-679LD (Tg point: 205° C. to 215° C.) orMCL-E-679F (Tg point: 205° C. to 217° C.) manufactured by HitachiChemical or R-5715 (Tg point: 190° C.) manufactured by MatsushitaElectric Works.

An opening is, by a laser beam or drilling, formed in the foregoingglass epoxy resin substrate or the copper-plated laminated board,followed by metalizing the surface of the inner wall by electricplating, electroless plating, sputtering or evaporation. Thus, thethrough hole is formed. A filler may be enclosed in the foregoingthrough hole.

The metalized inner wall of the through hole may be coarsened.

The filler may be made of any one of a variety of materials includinginorganic particles made of bis phenol F epoxy resin, silica or alumina;or metal particles; and resin.

The conductive circuit is provided for the thus-formed substrate havingthe through hole formed therein. The conductive circuit is formed by anetching process.

It is preferable that the surface of the conductive circuit is subjectedto the coarsening process.

Then, the interlayer insulating resin layer is formed. The insulatingresin may be thermosetting resin, thermoplastic resin or their compositeresin.

To solve the problem, in claim 46, a method of manufacturing a printedcircuit board incorporating through holes and conductor patterns formedby a subtractive method, said method of manufacturing a printed circuitboard according to the present invention comprising:

an opening forming step for forming an opening for forming a throughhole at a predetermined position of a metal-applied board formed byapplying conductive metal foil having a thickness of 0.5 μm to 7.0 μm toeach of two sides of an insulating substrate;

a desmear step for dissolving and removing smear existing in the openingfor forming the through hole;

a first plating step for forming a thin plated layer on a ground layercaused from the conductive metal foil and the surface of the inner wallof the opening for forming the through hole;

a second plating step for forming a mask on the thin plated layer andforming a thick plated layer on a portion exposed through an opening ofthe mask; and

performing etching after the mask has been separated so that the thinplated layer and the ground layer below the mask are removed so as todivide the conductor patter.

An aspect of claim 46 enables smear taken place during an openingforming process to be dissolved and removed by performing a desmearprocess. Also the conductive metal foil is dissolved and removed at thistime. Thus, the conductive metal foil is thinned. A first platingprocess is performed so that a thin plated layer is formed. Then, asecond plating process is performed so that a thick plated layer isformed. As a result, only portions which will be formed into theconductive pattern are selectively thickened. Then, etching is performedso that the thin plated layer below the mask and the ground layer areremoved. Thus, the conductive pattern is divided. In the presentinvention, both of the thin plated layer and the ground layer are thinlayers. Therefore, the thickness which must be removed by etchingperformed in the conductive pattern dividing step is very small.Therefore, formation of a divergent shape of the conductive patternformed by dividing does not easily occur. Thus, a fine pattern having asatisfactory shape can accurately be formed.

The conductive metal foil can be made with copper, aluminum, gold,silver, platinum or nickel. Specifically, the copper or the metal mainlycomprising the copper is desirable.

The present invention in claim 48 according to claim 48, the firstplating step uses an electroless plating bath, and the second platingstep uses an electrolytic plating bath.

An aspect of claim 48 has a structure that the electroless plating bathis employed only when the plated layer is formed on the inner wall ofthe opening for forming the through hole. Then, the low-costelectrolytic plating bath which exhibits high speed plating depositionspeed is employed. As a result, the cost reduction can be realized andthe productivity can be improved.

The present invention in claim 49 according to claim 47, the firstplating step uses an electroless copper plating bath to form a copperplated layer having a thickness of 0.2 μm to 2.5 μm, and the secondplating step uses an electrolytic copper plating bath to form a copperplated layer having a thickness of 8.0 μm or greater.

An aspect of claim 49 has a structure that the electroless plating bathis employed only when the plated layer is formed on the inner wall ofthe opening for forming the through hole. Then, the low-costelectrolytic plating bath which exhibits high speed plating depositionspeed is employed. As a result, the cost reduction can be realized andthe productivity can be improved. Since a very thin copper plated layeris formed in the first plating step, the thickness which must be removedby etching in the conductive pattern dividing step is very small.Therefore, a fine pattern having a satisfactory shape can furthermoreaccurately be formed.

The present invention in claim 50 according to any of claims 47 to 49,the step for dividing the conductor pattern by performing etching isperformed in a state in which no etching resist is provided for thethick plated layer formed in the second plating step.

An aspect of claim 50 has a structure that the step for forming andseparating the etching resist in the conductive pattern dividing stepcan be omitted. Thus, the number of manufacturing steps can be reducedand the productivity can be improved. Moreover, the thickness of thethick plated layer which is removed when the etching process isperformed is very small. Thus, no adverse influence is exerted on theaccuracy of the formed pattern.

According to another aspect of the present invention in claim 51, aprinted circuit board incorporating a conductive pattern is providedwhich is formed by, for example, subtractive method, wherein theconductive pattern includes a metal ground layer provided for aninsulating substrate and having a thickness of 0.2 μm to 3.0 μm and aplated layer formed on the metal ground layer.

According to another aspect of the present invention in claim 52, thereis a printed circuit board provided, wherein the conductive patternincludes a metal ground layer provided for an insulating substrate andhaving a thickness of 0.2 μm to 2.5 μm, a plated layer formed on themetal ground layer and having a thickness of 0.2 μm to 2.5 μm and aplated layer formed on the plated layer and having a thickness of 8.0 μmor greater.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 (A), 1 (B), 1 (C) and 1 (D) are diagrams showing a process formanufacturing a printed circuit board according to a first embodiment ofthe present invention;

FIGS. 2 (E), 2 (F), 2 (G) and 2 (H) are diagrams showing a process formanufacturing the printed circuit board according to the firstembodiment of the present invention;

FIGS. 3 (I), 3 (J), 3 (K) and 3 (L) are diagrams showing a process formanufacturing the printed circuit board according to the firstembodiment of the present invention;

FIGS. 4 (M), 4 (N), 4 (O) and 4 (P) are diagrams showing a process formanufacturing the printed circuit board according to the firstembodiment of the present invention;

FIGS. 5 (M′), 5 (N′), 5 (O′) and 5 (P′) are diagrams showing a processfor manufacturing the printed circuit board according to a firstmodification of the first embodiment of the present invention;

FIGS. 6 (Q) and 6 (R) are diagrams showing a process for manufacturingthe printed circuit board according to the first embodiment of thepresent invention;

FIGS. 7 (A), 7 (B) and 7 (C) are diagrams showing a process formanufacturing a multilayered printed circuit board according to a secondembodiment of the present invention;

FIGS. 8 (D), 8 (E) and 8 (F) are diagrams showing a process formanufacturing the multilayered printed circuit board according to thesecond embodiment;

FIGS. 9 (G), 9 (h) and 9 (I) are diagrams showing a process formanufacturing the multilayered printed circuit board according to thesecond embodiment of the present invention;

FIGS. 10 (J), 10 (K) and 10 (L) are diagrams showing a process formanufacturing the multilayered printed circuit board according to thesecond embodiment of the present invention;

FIGS. 11 (M) and 11 (N) are diagrams showing a process for manufacturingthe multilayered printed circuit board according to the secondembodiment of the present invention;

FIGS. 12 (A), 12 (B) and 12 (C) are diagrams showing a process formanufacturing a multilayered printed circuit board according to a firstmodification of the second embodiment of the present invention;

FIG. 13 is a diagram showing a process for manufacturing themultilayered printed circuit board according to the first modificationof the second embodiment of the present invention;

FIG. 14 is a plan view showing an example of a coarsened surface formedon a substrate according to a third embodiment of the present inventionby a coarsening method according to the present invention;

FIG. 15 is a vertical cross sectional view taken along line A-A andshowing the surface of the (D) shown in FIG. 14;

FIG. 16 is a vertical cross sectional view showing another portion ofthe surface of the (D) shown in FIG. 14;

FIGS. 17 (A), 17 (B), 17 (C) and 17 (D) are vertical cross sectionalviews showing a portion of a process for manufacturing a multilayeredprinted circuit board according to a third embodiment of the presentinvention;

FIGS. 18 (A), 18 (B), 18 (C) and 18 (D) are vertical cross sectionalviews showing a portion of a process for manufacturing the multilayeredprinted circuit board according to the third embodiment of the presentinvention;

FIGS. 19 (A), 19 (B), 19 (C) and 19 (D) are vertical cross sectionalviews showing a portion of the process for manufacturing themultilayered printed circuit board according to the third embodiment ofthe present invention;

FIG. 20 is a perspective view showing an opening for forming a via holewhich is formed in the printed circuit board according to the thirdembodiment of the present invention;

FIG. 21 is a cross sectional view showing the opening for forming thevia hole which is formed in the printed circuit board according to thethird embodiment of the present invention realized after a coarseningprocess has been performed;

FIGS. 22 (A), 22 (B), 22 (C) and 22 (D) are diagrams showing a processfor manufacturing a multilayered printed circuit board according to afourth embodiment of the present invention;

FIGS. 23 (E), 23 (F), 23 (G) and 23 (H) are diagrams showing a processfor manufacturing the multilayered printed circuit board according tothe fourth embodiment of the present invention;

FIGS. 24 (I), 24 (J), 24 (K) and 24 (L) are diagrams showing a processfor manufacturing the multilayered printed circuit board according tothe fourth embodiment of the present invention;

FIGS. 25 (M), 25 (N), 25 (O) and 25 (P) are diagrams showing a processfor manufacturing the multilayered printed circuit board according tothe fourth embodiment of the present invention;

FIGS. 26 (Q), 26 (R) and 26 (S) are diagrams showing a process formanufacturing the multilayered printed circuit board according to thefourth embodiment of the present invention;

FIG. 27 is a cross sectional view showing the multilayered printedcircuit board according to the fourth embodiment of the presentinvention;

FIG. 28 is a cross sectional view showing the multilayered printedcircuit board according to the fourth embodiment of the presentinvention;

FIG. 29 is an enlarged view showing a portion (C) shown in FIG. 24 (I);

FIG. 30 (A) is a sketch of an enlarged photograph of a through holeformed in an interlayer insulating resin layer when the through hole isviewed from a diagonally upper position, and FIG. 30 (B) is a sketchwhen the through hole is viewed from a position directly above thethrough hole;

FIG. 31 (A) is an enlarged view showing portion A shown in FIG. 26 (R),and FIG. 31 (B) is an enlarged view showing a portion B shown in FIG. 26(R);

FIG. 32 (A) is a sketch of an enlarged photograph of the through hole(upper portion) formed in a solder resist in a state in which thethrough hole is viewed from a diagonally upper position, and FIG. 32 (B)is a sketch of a state when the through hole is viewed from a positiondirectly above the through hole;

FIG. 33 (A) is a sketch of an enlarged photograph of the through hole(lower portion) formed in the solder resist in a state in which thethrough hole is viewed from a position directly above the through hole,FIG. 33 (B) is a sketch of a state when the side wall of the throughhole is viewed from a side position, and FIG. 33 (C) is a sketch of astate when the through hole is viewed from a diagonally upper position;

FIG. 34 is a diagram showing a laser unit for forming a through hole;

FIGS. 35 (A), 35 (B), 35 (C) and 35 (D) are diagrams showing a processfor manufacturing a substrate having a through hole formed thereinaccording to a first modification of a fifth embodiment;

FIGS. 36 (A), 36 (B), 36 (C) and 36 (D) are diagrams showing a processfor manufacturing a substrate having a through hole formed thereinaccording to a second modification of the fifth embodiment;

FIGS. 37 (A), 37 (B), 37 (C) and 37 (D) are diagrams showing a processfor manufacturing a substrate having a through hole formed thereinaccording to a third modification of the fifth embodiment;

FIGS. 38 (A), 38 (B), 38 (C), 38 (D), 38 (E) and 38 (F) are diagramsshowing a process for manufacturing a multilayered printed circuit boardaccording to a fourth modification of the fifth embodiment;

FIGS. 39 (G), 39 (H), 39 (I), 39 (J) and 39 (K) are diagrams showing aprocess for manufacturing a multilayered printed circuit board accordingto a fourth modification of the fifth embodiment;

FIGS. 40 (L), 40 (M), 40 (N), 40 (O) and 40 (P) are diagrams showing aprocess for manufacturing a multilayered printed circuit board accordingto the fourth modification of the fifth embodiment;

FIGS. 41 (Q), 41 (R), 41 (S) and 41 (T) are diagrams showing a processfor manufacturing a multilayered printed circuit board according to thefourth modification of the fifth embodiment;

FIGS. 42 (U), 42 (V) and 42 (W) are diagrams showing a process formanufacturing a multilayered printed circuit board according to thefourth modification of the fifth embodiment;

FIG. 43 is a cross sectional view showing the multilayered printedcircuit board according to the fourth modification of the fifthembodiment;

FIG. 44 is a cross sectional view showing a multilayered printed circuitboard according to a sixth embodiment of the fifth embodiment;

FIGS. 45 (A), 45 (B), 45 (C), 45 (D), 45 (E) and 45 (E′) are diagramsshowing a process for manufacturing a multilayered printed circuit boardaccording to a sixth embodiment of the present invention;

FIGS. 46 (F), 46 (G), 46 (H), 46 (I), 46 (J) and 46 (K) are diagramsshowing a process for manufacturing the multilayered printed circuitboard according to the sixth embodiment of the present invention;

FIGS. 47 (L), 47 (M), 47 (N), 47 (O) and 47 (P) are diagrams showing aprocess for manufacturing the multilayered printed circuit boardaccording to the sixth embodiment of the present invention;

FIGS. 48 (Q),48 (R), 48 (S) and 48 (T) are diagrams showing a processfor manufacturing the multilayered printed circuit board according tothe sixth embodiment of the present invention;

FIGS. 49 (U) and 49 (V) are cross sectional views showing the multilayered printed circuit board according to the sixth embodiment of thepresent invention;

FIG. 50 is a cross sectional view showing the multilayered printedcircuit board according to the sixth embodiment of the presentinvention;

FIGS. 51 (A), 51 (B) and 51 (C) are partial and schematic crosssectional views showing a copper-plated laminated board for use tomanufacture a printed circuit board according to a seventh embodiment;

FIGS. 52 (A) and 52 (B) are partial and schematic cross sectional viewsshowing the copper-plated laminated board for use to manufacture theprinted circuit board according to the seventh embodiment;

FIGS. 53 (A) and 53 (B) are partial and schematic cross sectional viewsshowing the copper-plated laminated board for use to manufacture theprinted circuit board according to the seventh embodiment;

FIG. 54 is a partial and schematic cross sectional view showing amultilayered printed circuit board according to a first modification ofthe seventh embodiment;

FIG. 55 is a partial and schematic cross sectional view showing themultilayered printed circuit board according to the first modificationof the seventh embodiment;

FIG. 56 is a graph showing a result of a comparison between the secondembodiment and a comparative example;

FIG. 57 is a graph showing a result of a comparison between the thirdembodiment and a comparative example;

FIG. 58 is a graph showing a result of a comparison between the sixthembodiment and a comparative example;

FIG. 59 is a diagram showing a chemical formula; and

FIG. 60 is a diagram showing a chemical formula.

DETAILED DESCRIPTION First Embodiment

A method of manufacturing a multilayered printed circuit board accordingto a first embodiment of the present invention will now be describedwith reference to the drawings.

(1) A copper-plated laminated board 30A is used as a start material (seeFIG. 1 (A)) incorporating a substrate 30 having a thickness of 1 mm andmade of glass epoxy resin or BT (bis maleimide-triazine) resin andcopper foil 32 having a thickness of 18 μm laminated on the two sides ofthe substrate 30. Initially, an opening is formed in the copper-platedlaminated board 30A by drilling, followed by subjecting the same to anelectroless plating process, and followed by etching the same inaccordance with the pattern. Thus, an inner layer copper pattern 34 anda through hole 36 are provided for the two sides of the substrate 30(see FIG. 1 (B)).

(2) The substrate 30 having the inner-layer copper pattern 34 and thethrough hole 36 is cleaned with water, and then dried. Then, anoxidizing bath composed of NaOH (10 g/l), NaClO₂ (40 g/l) and Na₃PO₄ (6g/l) and a reducing bath composed of NaOH (10 g/l) and NaBH₄ (6 g/l) areused to perform an oxidizing and reducing process so that a coarsenedlayer 38 is formed on the surface of each of the inner-layer copperpattern 34 and the through hole 36 (see FIG. 1 (C)).

(3) The following raw-material compositions for preparing a resin fillerare mixed and kneaded so that a resin filler is obtained.

[Resin Composition (1)] 100 parts by weight of Bis phenol F epoxymonomer (YL983U manufactured by Yuka Shell and having a molecular weightof 310), 170 parts by weight of SiO₂ spherical particle (CRS1101-CE andthe size of the maximum particle is smaller than the thickness (15 μm)of an inner-layer copper pattern to be described later) each having asurface coated with a silane coupling agent and an average particle sizeof 1.6 μm and 1.5 parts by weight of a leveling agent (Pelenol S4manufactured by Sunnopko) are mixed and stirred. Thus, the viscosity ofthe mixture is adjusted to be 45,000 cps to 49,000 cps at 23±1° C. Thus,the foregoing composition is obtained.

[Hardener Composition (2)]

6.5 parts by weight of imidazole hardener (2E4MZ-CN manufactured byShikoku Kasei)

(4) The resin filler 40 obtained in the process (3) is applied to thetwo sides of the substrate 30 by using a roll coater within 24 hoursafter the adjustment. Thus, the resin filler 40 is enclosed between theconductive circuit (the inner-layer copper pattern) 34 and theconductive circuit 34 and in the through hole 36. Then, the resin filler40 is dried at 70° C. for 20 minutes. Another side is similarlyprocessed. Thus, the resin filler 40 is enclosed between the conductivecircuits 34 or in the through hole 36, and then heated and dried at 70°C. for 20 minutes (see FIG. 1 (D)).

(5) Either side of the substrate 30 subjected to the process (4) isbelt-sander-polished by using #600 belt polishing paper (manufactured bySankyo). Thus, polishing is performed such that the resin filler 40 isnot left on the surface of the inner-layer copper pattern 34 and thesurfaces of lands 36 a of the through hole 36. Then, flaws caused fromthe belt-sander-polishing were removed by performing buff polishing. Theforegoing sequential polishing process is performed for another surface(see FIG. 2 (E)).

Then, heat treatment was performed at 100° C. for 1 hour, 120° C. for 3hours, 150° C. for 1 hour and 180° C. for 7 hours. Thus, the resinfiller 40 was hardened.

(6) The substrate 30 having the conductive circuit 34 was degreased byusing alkali material, and soft etching was performed. Then, a processusing a catalyst composed of palladium chloride and organic acid wasperformed so that a Pd catalyst was imparted. Then, the catalyst wasactivated, and then the substrate was immersed in electroless platingsolution composed of 3.2×10⁻² mol/l copper sulfate, 3.9×10⁻³ mol/lnickel sulfate, 5.4×10⁻² mol/l complexing agent, 3.3×10⁻¹ mol/l sodiumhypophosphite, 5.0×10⁻¹ mol/l boric acid and a 0.1 g/l surface activeagent (Surfil 465 manufactured by Nissin Chemical Industry) having PH=9.After a lapse of one minute from the immersion, the substrate wasvertically and laterally vibrated one time at intervals of four seconds.Thus, a coating layer made of a needle alloy composed of Cu—Ni—P and acoarsened layer 42 were formed on the surface of the conductive circuit34 and the land 36 a of the through hole 36 (see FIG. 2 (F)).

Then, 0.1 mol/l tin borofluoride and 1.0 mol/l thiourea were used at atemperature of 35° C. and PH=1.2 so that Cu—Sn substitution reactionswere performed. Thus, a Sn layer (not shown) having a thickness of 0.3μm was formed on the surface of the coarsened layer.

(7) Then, copper foil having resin (MCF-6000E manufactured by HitachiKasei and including resin 20 having a thickness of 60 μm and copper foil22 having a thickness of 12 μm) 20A is pressed against to the two sidesof the substrate 30 having the thickness of 0.8 mm by operating a vacuumpressing machine (see FIG. 2 (G)), the vacuum pressing operation beingperformed under conditions that the temperature is 175° C. for 90minutes, the pressure is 30 Kg/cm2 and the degree of vacuum <50 torr).

(8) Then, the overall surface of the surface copper foil 22 is etched tomake the thickness to be 3 μm by using etching solution (SE-07manufactured by Mitsubishi Gas) (see FIG. 2 (H)).

(9) A dry-film resist (NIT-215 manufactured by NichigoMoton) is appliedto the copper foil 22, and then a mask is placed. Then, exposure isperformed with 100 mJ/cm2 and a development process is performed byusing 0.8% sodium carbonate. Thus, an etching resist 43 having anopening 43 a formed in a portion in which the via hole will be formed isprovided (see FIG. 3 (I)).

(10) The copper foil 22 in the opening 43 a is removed by cupricchloride etching solution (see FIG. 3 (J)), and then the etching resist43 is separated by sodium hydroxide solution so that copper foil 22serving as the conformal mask is completed (see FIG. 3 (K)).

(11) A carbon-dioxide gas laser irradiating apparatus 605GTXmanufactured by Mitsubishi Electric) is operated to irradiate eachopening 22 a of the copper foil with a two-shot and short-pulse laserbeam so that a through hole 20 a having a diameter of 60 μm is formed inthe interlayer insulating resin layer (resin) 20 (see FIG. 3 (L)). Thatis, the copper foil 22 having the thickness of 3 μm is used as theconformal mask to form the opening 22 a by applying the laser beam. Theirradiation with the carbon-dioxide gas laser may be performed for eachopening 22 a of the copper foil 22 or the overall portion of the printedcircuit board is irradiated and scanned with the laser beam to removethe resin 20 in the lower portion of each opening 22 a of the copperfoil 22.

It is preferable that the diameter of the laser beam is 1.3 times ormore the diameter of the opening. After the opening 20 a has beenformed, residues may be removed. For example, immersion in solution of,for example, chromic acid, permanganic acid or potassium or use of O₂plasma, CF₄ plasma or plasma of mixture gas of O₂ and CF₄ enables theresidues to be removed. When fluorine resin is employed to form theinterlayer insulating resin layer, the plasma process is an optimumprocess.

(12) Usual electroless plating of the surface of the substrate 30 isperformed so that an electroless copper plated film 52 was formed on thesurface of the substrate 30 (see FIG. 4 (M)). Then, copper sulfateplating is performed so that an electrolytic copper plated film 56having a thickness of 10 μm is formed (see FIG. 4 (N)).

(13) A dry film resist (NIT-215 manufactured by NichigoMorton) isapplied to the copper foil 22, and then a mask (not shown) having apattern formed at a predetermined position thereof is placed. Then,exposure is performed with 100 mJ/cm2. Then, a development process isperformed by using 0.8% sodium carbonate so that an etching resist 54for covering the portion in which the via hole will be formed and aportion in which a circuit will be formed and having a structure ofLine/Space: 30/30 μm is formed (see FIG. 4 (O)).

(14) Then, cupric chloride is used to perform pattern etching. Then, 2%NaOH s used to separate the etching resist 54 so that a via hole 60 anda conductive circuit 58 are formed (see FIG. 4 (P)).

As an alternative to the foregoing procedure in the processes (12) to(14) that the resist 54 is formed after the electrolytic copper plating56 has been formed, the electrolytic copper plating 56 may be formedafter the resist 54 has been formed. A manufacturing process accordingto a first modification will now be described with reference to FIG. 5.

Initially, the substrate 30 having the resin 20 having the opening 20 aand shown in FIG. 3 (L) is immersed in the electroless copper platingbath having the following solution so that an electroless copper platedfilm 52 having a thickness of 0.5 μm is formed (see FIG. 5 (M′)).

Electroless Plating Solution

EDTA 150 g/l Copper Sulfate  20 g/l HCHO  30 ml/l NaOH  40 g/la,a′-Bipyridyl  80 mg/l PEG  0.1 g/l

Conditions of Electroless Plating

30 minutes when the temperature of the solution is 70° C.

A dry-film resist (NIT-215 manufactured by NichigoMoton) is applied tothe copper foil 22, and then a mask (not shown) is placed. Then,exposure is performed with 100 mJ/cm² and a development process isperformed by using 0.8% sodium carbonate. Thus, an etching resist 54having an opening 54 a formed in a portion in which the via hole will beformed and a portion in which the circuit will be formed is provided(see FIG. 5 (N′)).

Then, electrolytic copper plating is performed under the followingconditions so that an electrolytic copper plating film 56 is formedwhich has a thickness of 20 μm (see FIG. 5 (O′)).

Electrolytic Plating Solution

Sulfuric Acid 180 g/l Copper Sulfate  80 g/l Additive (Capalacid GLmanufactured  1 ml/l by Attech Japan)

Conditions of Electrolytic Plating

Density of Current  1 A/dm² Time 30 minutes Temperature room temperature

The plating resist 54 is removed by using 5% KOH, and then mixedsolution of sulfuric acid and hydrogen peroxide is used to performetching so that the electroless copper plated film 52 and the copperfoil 22 under the plating resist 54 are dissolved and removed. Thus, aconductive circuit 58 composed of the copper foil 20, the electrolesscopper plated films 30 and 40 and the electrolytic copper plated film 44and having a thickness of 18 μm and the via hole 60 are formed (see FIG.5 (P′)).

(15) Finally, a process similar to the process (6) is performed so thata coarsened surface 62 made of Cu—Ni—P is formed on the surface of eachof the conductive circuit 58 and the via hole 60. Then, the Snsubstituting of the surface is performed (see FIG. 6 (Q)).

(16) The foregoing processes (7) to (15) are repeated so that an upperconductive circuit 88 and a via hole 90 are formed. Thus, a multilayeredprinted circuit board is obtained (see FIG. 6 (R)). Note the Snsubstitution of the coarsened surface formed on the surfaces of theconductive circuit 88 and the via hole 90 is not performed.

In the first embodiment, the metal film (the copper foil) 22, thethickness of which has been reduced (3 mm) by etching and the thermalconductivity of which has been lowered is used as the conformal mask.Therefore, the opening 20 a can be formed by a small-output laser.Specifically, the conventional manufacturing method is required to applya short pulse laser beam three times to form one opening 20 a in theresin 20 by the foregoing carbon-dioxide gas laser apparatus. On theother hand, the first embodiment is able to form the opening 20 a byapplying two short-pulse laser beams.

The first embodiment is able to form the opening 20 a with thesmall-output laser or such that the number of operations for applyingthe pulse laser beams is reduced. Therefore, occurrence of undercut inthe resin 20 for forming interlayer insulating resin layer can beprevented (see FIG. 3 (L)). Therefore, the reliability of the connectionof the via hole can be improved. It is preferable that the thickness ofthe metal film is reduced to 5 μm to 0.5 μm by etching. If the thicknessof the metal film is larger than 5 μm, undercut occurs. If the thicknessis not larger than 0.5 μm, the function of the conformal mask cannot berealized.

When the interlayer insulating resin layer forming resin having themetal film formed thereon is pressed against the substrate on which theconductive circuit will now be formed and then etching is performed, thethick metal film exists as a reinforcing member until the pressingoperation is performed. Therefore, an excellent handling characteristiccan be obtained.

In this embodiment, the interlayer insulating resin layer forming resinhaving the metal film formed thereon is pressed, and then etching isperformed. Note that the interlayer insulating resin layer forming resinhaving a thin metal film having a thickness of 5 μm to 0.5 μm may bepressed.

In the first embodiment, the metal film which is used as the conformalmask is etched so as to be thinned. When the conductive circuit 58 andthe via hole 60 are formed, the conformal mask 30 in an unnecessaryportion is removed by etching. Since the conformal mask 30 has a smallthickness, it can easily be reduced. Therefore, the foregoing etchingoperation does not result in excessive corrosion of the electrolyticcopper plated film 56 for forming the conductive circuit 58 and the viahole 60. Therefore, a circuit having a fine pitch and a via hole havinga precise diameter can be formed. The conventional manufacturing methodhas been able to form a circuit having a size of 75 μm. On the otherhand, the first embodiment is able to improve the performance to 50 μm.The conventional technique has been able to form the conformal maskhaving a diameter of 50 μm. On the other hand, the first embodiment isable to form an opening having a diameter of 13 μm. Therefore, a viahole having a small diameter can be formed.

A method of manufacturing a multilayered printed circuit board accordingto a second modification of the first embodiment will now be described.The second modification employs similar process to that of themanufacturing method according to the first embodiment except foremployed base member. Therefore, the description will be made withreference to FIGS. 1 to 6.

The foregoing processes (1) to (6) are performed so that a coresubstrate 30 structured as shown in FIG. 2 (F) and having a thickness of0.4 mm is formed. Then, copper foil with resin (ARCC-0880 manufacturedby Matsushita Electronics, the thickness of the resin 20 is 60 μm andthe thickness of the copper foil is 12 μm) 20A is pressed against thetwo sides of the substrate 30 by operating a vacuum pressing machine(see FIG. 2 (G)), the vacuum pressing operation being performed underconditions that the temperature is 130° C. for 30 minutes and 175° C.for 90 minutes, the pressure is 30 Kg/cm² and the degree of vacuum <50torr.

Then, the overall surface of the surface copper foil 22 is etched tomake the thickness to be 3 mm by using etching solution (SE-07manufactured by Mitsubishi Gas) (see FIG. 2 (H))

A dry-film resist (NIT-215 manufactured by NichigoMoton) is applied tothe copper foil 22, and then a mask is placed. Then, exposure isperformed with 100 mJ/cm² and a development process is performed byusing 0.8% sodium carbonate. Thus, an etching resist 44 having anopening 44 a formed in a portion in which the via hole will be formed isprovided (see FIG. 3 (I)).

The copper foil 22 in the opening 44 a is removed by cupric chlorideetching solution (see FIG. 3 (J)), and then the etching resist 44 isseparated by sodium hydroxide solution so that copper foil 22 serving asthe conformal mask is completed (see FIG. 3 (K)).

A carbon-dioxide gas laser irradiating apparatus (605GTX manufactured byMitsubishi Electric) is operated to irradiate each opening 22 a of thecopper foil with a two-shot and short-pulse laser beam so that a throughhole 20 a having a diameter of 60 μm is formed in the interlayerinsulating resin layer (resin) 20 (see FIG. 3 (L)).

An electroless copper plated film 52 is formed on the surface of thesubstrate 30 by usual electroless plating (see FIG. 4 (M)). Then, coppersulfate plating is performed so that an electrolytic copper plated film56 having a thickness of 10 μm is formed (see FIG. 4 (N)).

A dry film resist (NIT-215 manufactured by NichigoMorton) is applied tothe copper foil 22, and then a mask (not shown) having a pattern formedat a predetermined position thereof is placed. Then, exposure isperformed. Then, a development process is performed by using 0.8% sodiumcarbonate so that an etching resist 54 for covering the portion in whichthe via hole will be formed and a portion in which a circuit will beformed and having a structure of Line/Space: 50/50 μm is formed (seeFIG. 4 (O)).

Then, cupric chloride is used to perform pattern etching. Then, 2% NaOHis used to separate the etching resist 54 so that a via hole 60 and aconductive circuit 58 are formed (see FIG. 4 (P)). Then, similarprocesses are repeated so that a printed circuit board having six layersformed on the two sides is manufactured (see FIG. 6 (R)).

A method of manufacturing a multilayered printed circuit board accordingto a third modification of the first embodiment will now be described.The third modification employs similar processes to those of themanufacturing method according to the first embodiment except for theemployed base member. Therefore, the description will be made withreference to FIGS. 1 to 6.

The foregoing processes (1) to (6) are performed so that a coresubstrate 30 shown in FIG. 2 (F) and a thickness of 0.6 mm is formed.Then, copper foil with resin including glass cloth (CCL-HL830LSmanufactured by Mitsubishi Gas, the thickness of the glass cloth/resin20 is 60 μm and the thickness of the copper foil 22 is 12 μm) 20A ispressed to each of the two sides of the substrate 30 by a vacuumpressing machine (see FIG. 2 (G)). The vacuum pressing operation isperformed under conditions that the temperature is 150° C. for 30minutes and the temperature is 175° C. for 90 minutes, the pressure is30 Kg/cm² and the degree of vacuum <50 torr.

Then, the overall surface of the surface copper foil 22 is etched tomake the thickness to be 3 mm by using etching solution (SE-07manufactured by Mitsubishi Gas) (see FIG. 2 (H)).

A dry-film resist (NIT-215 manufactured by NichigoMoton) is applied tothe copper foil 22, and then a mask is placed. Then, exposure isperformed with 100 mJ/cm² and a development process is performed byusing 0.8% sodium carbonate. Thus, an etching resist 44 having anopening 44 a formed in a portion in which the via hole will be formed isprovided (see FIG. 3 (I)).

The copper foil 22 in the opening 44 a is removed by cupric chlorideetching solution (see FIG. 3 (J)), and then the etching resist 44 isseparated by sodium hydroxide solution so that copper foil 22 serving asthe conformal mask is completed (see FIG. 3 (K)).

A carbon-dioxide gas laser irradiating apparatus (605GTX manufactured byMitsubishi Electric) is operated to irradiate each opening 22 a of thecopper foil with a two-shot and short-pulse laser beam so that a throughhole 20 a having a diameter of 60 μm is formed in the interlayerinsulating resin layer (resin) 20 (see FIG. 3 (L)).

An electroless copper plated film 52 is formed on the surface of thesubstrate 30 by usual electroless plating (see FIG. 4 (M)). Then, coppersulfate plating is performed so that an electrolytic copper plated film56 having a thickness of 10 μm is formed (see FIG. 4 (N)).

A dry film resist (NIT-215 manufactured by NichigoMorton) is applied tothe copper foil 22, and then a mask (not shown) having a pattern formedat a predetermined position thereof is placed. Then, exposure isperformed. Then, a development process is performed by using 0.8% sodiumcarbonate so that an etching resist 54 for covering the portion in whichthe via hole will be formed and a portion in which a circuit will beformed and having a structure of Line/Space: 50/50 μm is formed (seeFIG. 4 (O)).

Then, cupric chloride is used to perform pattern etching. Then, 2% NaOHis used to separate the etching resist 54 so that a via hole 60 and aconductive circuit 58 are formed (see FIG. 4 (P)). Then, similarprocesses are repeated so that a printed circuit board having six layersformed on the two sides is manufactured (see FIG. 6 (R)).

In the foregoing embodiment, the resin to which the copper foil has beenallowed to adhere to is employed. Note that a metal film, such as copperfoil, may afterwards be bonded to the resin. In the first and secondmodification, the resin to which the copper foil has been allowed toadhere to is employed. In the third modification, the resin includingglass cloth to which the copper foil has been allowed to adhere to isemployed. Resin to which any one of a variety of materials (for example,unwoven fabric) has been added may be employed.

As described above, according to the first embodiment, the opening forforming the via hole can be formed by using a small-output laser or byreducing the number of the irradiation operations of the pulse laserbeams. Therefore, occurrence of undercut of the resin for forming theinterlayer insulating resin layer can be prevented. Therefore, thereliability of the connection of the via hole can be improved.

Second Embodiment

A multilayered printed circuit board and a manufacturing method thereforaccording to a second embodiment of the present invention will now bedescribed.

As the substrate for use in the second embodiment may be a resinsubstrate, such as a glass-cloth epoxy resin substrate, a glass-clothbis maleimide-triazine resin, glass-cloth fluorine resin substrate; acopper-plated laminated board obtained by bonding copper foil to theforegoing resin substrate, a metal substrate or a ceramic substrate.

A conductive circuit is provided for the upper surface of the substrate.The conductive circuit can be formed by electroless plating orelectrolytic plating. When the copper-plated laminated board isemployed, the conductive circuit can be formed by an etching process.

Then, an insulating resin layer is formed. In the second embodiment, theinsulating resin layer is irradiated with a laser beam so that anopening for forming the via hole is formed. Therefore, the foregoinginsulating resin layer is made of a material with which the opening canbe formed by applying the laser beam.

The foregoing material is thermosetting resin, thermoplastic resin ortheir composite resin.

For example, an adhesive agent for electroless plating may be employed,the basic material of which is thermosetting resin. The thermosettingresin is any one of epoxy resin, phenol resin and polyimide resin. Thethermoplastic resin may be anyone of polyether sulfone (PES),polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide(PPES), polyphenyl ether (PPE), polyetherimide (PI) and fluorine resin.

In the second embodiment, the coarsened surface of the metal layer orthe insulating resin layer exposed over the metal foil is formed by thefollowing method.

Specifically, particles which can be dissolved with acid or an oxidizingagent is previously contained in the insulating resin layer, followed bydissolving the particles with the acid or the oxidizing agent. Thus, thecoarsened surface can be formed on the insulating resin layer. In theforegoing case, a metal layer must be formed after the coarsened surfacehas been formed.

The foregoing heat-resisting resin particles may be heat-resisting resinparticles made of amino resin (melamine resin, urea resin or guanamineresin), epoxy resin (an optimum material is a resin obtained byhardening bisphenol type epoxy resin with an amine hardener) or bismaleimide-triazine resin.

The foregoing adhesive agent for electroless plating may containhardened heat-resisting resin particles, inorganic particles or a fiberfiller, if necessary.

The above heat resisting resin particles particularly hardened aredesirably constructed by using {circle around (1)} heat resisting resinpowder having an average particle diameter equal to or smaller than 10μm, {circle around (2)} cohesive particles formed by aggregating heatresisting resin powder having an average particle diameter equal to orsmaller than 2 μm, {circle around (3)} a mixture of heat resistingpowder resin powder having an average particle diameter from 2 to 10 μmand heat resisting resin powder having an average particle diameterequal to or smaller than 2 μm, {circle around (4)} pseudo-particles inwhich at least one kind of heat resisting resin powder or inorganicpowder having an average particle diameter equal to or smaller than 2 μmis attached to the surface of heat resisting resin powder having anaverage particle diameter from 2 to 10 μm, {circle around (5)} a mixtureof heat resisting powder resin powder having an average particlediameter from 0.1 to 0.8 μm and heat resisting resin powder having anaverage particle diameter greater than 0.8 μm and smaller than 2 gm, and{circle around (6)} heat resisting powder resin powder having an averageparticle diameter from 0.1 to 1.0 μm. This is because these materialscan form a more complicated anchor.

The coarsened surface of the insulating resin layer according to thesecond embodiment may be formed by using a metal foil having a coarsenedlayer, such as so-called RCC (RESIN COATED COPPER: copper foil withresin). In the foregoing case, the coarsened layer is formed on eitherside of the metal foil, and the insulating resin layer is formed on thecoarsened layer. Thus, the metal foil is formed.

The coarsened layer on the metal surface can be formed by any one of avariety of coarsening processes. The coarsening process is exemplifiedby an etching process including a matting process, an oxidizing process,an oxidizing and reducing process, a blackening and reducing process, asulfuric acid and hydrogen peroxide process and a process using cupriccomplex and organic acid or a plating process, such as a needle alloyplating using copper, nickel and phosphorus.

The thus-formed metal foil is laminated on a lower conductive circuitprovided for the core substrate. At this time, the surface of theinsulating resin layer and the lower conductive circuit is brought intocontact with each other. Moreover, the core substrate and the metal foilare heated and compressed so as to be integrated with each other.

When the metal foil is removed by etching, the coarsened surface causedfrom the coarsened layer can be transferred to the surface of theexposed insulating resin layer.

As the etching solution which is employed in a case of the copper foil,sulfuric acid-hydrogen peroxide solution, ammonium persulfate solutionor ferric chloride may be employed.

It is preferable that the coarsened surface which is formed on thesurface of the insulating resin layer or the coarsened layer which isformed on the surface of the copper foil has a maximum roughness (Rj) of0.01 μm to 5 μm. If the maximum roughness is smaller than 0.01 μm, thecoarsened surface which is formed on the surface of the insulating resinlayer or the coarsened surface which is transferred to the surface ofthe insulating resin layer can easily reflect the laser beam. As aresult, the insulating resin layer cannot sufficiently be removed. Ifthe maximum roughness is larger than 5 μm, the coarsened layer cannoteasily be removed by etching.

In the second embodiment, the thus-formed coarsened surface isirradiated with a laser beam to remove the insulating resin layer. Thus,an opening for forming the via hole is formed. When the opening isplated, the via hole can be formed.

The foregoing laser beam may be a carbon dioxide gas laser beam, anultraviolet laser beam or an eximer laser beam. In particular, thecarbon dioxide gas laser beam is a preferred laser beam because it canbe generated by a low-cost apparatus.

In the second embodiment, to improve the adhesiveness between the lowerconductive circuit and the insulating resin layer and that between thelower conductive circuit and the via hole conductor, it is preferablethat the coarsened surface is formed on the surface of the lowerconductive circuit.

The foregoing coarsened surface can be formed by any one of a variety ofcoarsening processes. The coarsening process is exemplified by anetching process including an oxidizing process, an oxidizing andreducing process, a blackening and reducing process, a sulfuric acid andhydrogen peroxide process and a process using cupric complex and organicacid or a plating process, such as a needle alloy plating using copper,nickel and phosphorus.

The lower conductive circuit easily encounters leaving of the resin onthe coarsened surface when the opening for forming the via hole isformed. The method according to the second embodiment is arranged toprovide the coarsened surface for the surface of the insulating resinlayer. Therefore, irradiation of the coarsened surface with the laserbeam enables the insulating resin layer to be removed without leaving ofthe resin on the coarsened surface of the lower conductive circuit.

Then, a catalyst, such as Pd catalyst, for electroless plating is addedto plate the inside portion of the opening for forming the via hole sothat the via hole is formed. Moreover, the conductive circuit isprovided for the surface of the insulating resin layer. The electrolessplated film is formed to the inner wall of the opening and the overallsurface of the insulating resin layer. Then, a plating resist is formed,and then electric plating is performed. The plating resist is removed sothat the conductive circuit is formed by etching.

A method of manufacturing the multilayered printed circuit boardaccording to the second embodiment will now be described with referenceto FIGS. 7 to 11.

Raw material composition substance for adjusting and manufacturing anadhesive for electroless plating

(1) A resin composition substance is obtained by stirring and mixing 35weight parts of a resin liquid, 3.15 weight parts of a photosensitivemonomer (manufactured by TO-A GOSEI, Alonix M315), 0.5 weight part of anantifoaming agent (manufactured by SAN-NOPUKO, S-65) and 3.6 weightparts of NMP. In the resin liquid, 25% of a cresol novolak type epoxyresin (manufactured by NIHON KAYAKU, molecular weight 2500) and 80 wt %of an acrylic substance in concentration.(2) A resin composition substance is obtained by mixing 12 weight partsof polyether sulfone (PES), 7.2 weight parts of epoxy resin particles(manufactured by SANYO KASEI, polymer pole) having an average particlediameter of 1.0 μm, and 3.09 weight parts of epoxy resin particleshaving an average particle diameter of 0.5 μm, and then adding 30 weightparts of NMP to the mixed material and stirring and mixing thesematerials by a beads mill.(3) A hardening agent composition substance is obtained by stirring andmixing 2 weight parts of an imidazole hardening agent (manufactured bySHIKOKU KASEI, 2E4MZ-CN), 2 weight parts of an optical starting agent(manufactured by CHIBAGAIGI, Irugacure I-907), 0.2 weight part of aphotosensitizer (manufactured by NIHON KAYAKU, DETX-S), and 1.5 weightparts of NMP.(4) The raw material composition substances (1) to (3) are adjusted tomanufacture the adhesive for electroless plating.

Preparation of Resin Filler

(1) 100 parts by weight of Bis phenol F epoxy monomer (YL983Umanufactured by Yuka Shell and having a molecular weight of 310), 170parts by weight of SiO₂ spherical particle (CRS1101-CE and the size ofthe maximum particle is smaller than the thickness (15 μm) of aninner-layer copper pattern to be described later) each having a surfacecoated with a silane coupling agent and an average particle size of 1.6μm and 1.5 parts by weight of a leveling agent (Pelenol S4 manufacturedby Sunnopko) are kneaded by the three-rod roll. Thus, the viscosity ofthe mixture is adjusted to be 45,000 cps to 49,000 cps at 23±1° C. Thus,the foregoing composition is obtained.

(2) 6.5 parts by weight of imidazole hardener (2E4MZ-CN manufactured byShikoku Kasei)

(3) The mixture (1) and (2) are mixed with each other so that the resinfiller was adjusted.

Manufacturing of Printed Circuit Board

(1) As shown in FIG. 7 (A), the second embodiment is structured suchthat a copper-plated laminated board 230A incorporating a substrate 230having a thickness of 1 mm and made of glass epoxy resin or bismaleimide-triazine (BT) resin. The two sides of the substrate 230 arelaminated with copper foil 232 having a thickness of 18 μm. Thesubstrate 230A was employed as the start material.

(2) Initially, a drill opening 233 as shown in FIG. 7 (B) is formed inthe copper-plated laminated board 230A, and then electroless plating andelectrolytic plating are performed. Moreover, the copper foil 232 isetched into a predetermined pattern by a known method. Thus, aninner-layer copper pattern (a lower conductive circuit) 234 having athickness of 25 μm and a through hole 236 were formed on the two sidesof the substrate 230.

Then, a coarsened surface 238 was provided for each of the surface ofthe inner-layer copper pattern 234, the surface of the land of thethrough hole 236 and the inner wall. Thus, a circuit board 230 as shownin FIG. 7 (B) was manufactured. The coarsened surface 238 was formed bycleaning the foregoing substrate with water, by drying the substrate, byspraying etching solution to the two sides of the substrate and byetching the surface of the inner-layer copper pattern 234, the surfaceof the land of the through hole 236 and the inner wall. The etchingsolution was a mixture of 10 parts by weight of imidazole copper (II)complex, 7 parts by weight of glycollic acid, 5 parts by weight ofpotassium chloride and 78 parts by weight of ion exchange water.

(3) Then, a resin layer 240 as shown in FIG. 7 (C) was provided for aspace between the inner-layer copper patterns 234 of the circuit board230 and the inside portion of the through hole 236. The resin layer 240was formed by coating the two sides of the circuit board 230 with aresin filler which has been prepared by using a roll coater and enclosedbetween the inner-layer copper patterns 234 and the inside portion ofthe through hole 236 and by performing heat treatment at 100° C. for 1hour, 120° C. for 3 hours, 150° C. for 1 hour and 180° C. for 7 hours.Thus, the resin filler was hardened.

(4) Either side of the substrate obtained in the process (3) wasbelt-sander-polished by using #600 belt polishing paper (manufactured bySankyo). Thus, leaving of the resin filler on the coarsened surface ofthe inner-layer copper pattern 234 and the surface of the land of thethrough hole 236 was prevented. Then, flaws caused from thebelt-sander-polishing were removed by performing buff polishing. Theforegoing sequential polishing process is performed for another surfaceso that a circuit board 230 shown in FIG. 7 (C) was obtained.

The obtained circuit board 230 has the resin layer 240 formed betweenthe inner-layer copper patterns 234. Moreover, the resin layer 240 isprovided for the inside portion of the through hole 236. The coarsenedsurface 238 of the inner-layer copper pattern 234 and the coarsenedsurface 238 of the surface of the land of the through hole 236 have beenremoved. Both of the sides of the substrate have been flattened by theresin filler. The resin layer 240 is brought into hermetic contact withthe coarsened surface 238 a of the side surface of the inner-layercopper pattern 234 or the coarsened surface 238 a of the side surface ofthe land portion of the through hole 236. The resin layer 240 is broughtinto hermetic contact with the coarsened surface 238 on the inner wallof the through hole 236.

(5) As shown in FIG. 8 (D), the exposed inner-layer copper pattern 234and the upper surface of the land of the through hole 236 are coarsenedby the etching process (2). Thus, a coarsened surface 242 having a depthof 3 μm was formed.

The coarsened surface 242 was tin-substituted so that a Sn layer havinga thickness of 0.3 μm was formed. The substitutional plating wasperformed under conditions that 0.1 mol/L of tin borofluoride and 1.0mol/L of thiourea were used at a temperature of 50° C. and pH was 1.2.Thus, the coarsened surface 242 was Cu—Sn-substituted (the Sn layer isomitted from illustration).

(6) The two sides of the obtained circuit board were coated withadhesive agent for electroless plating by using a roll coater. Thesubstrate coated with the adhesive agent was allowed to stand in ahorizontal state for 20 minutes, followed bump drying the substrate at60° C. for 30 minutes. Thus, an adhesive layer 250 structured as shownin FIG. 8 (E) and having a thickness of 35 μm was formed.

(7) The two sides of the obtained circuit board were exposed to light byusing an extra high tension mercury lamp with 500 mJ/cm², that is,heated at 150° C. for 5 hours.

(8) The obtained substrate was immersed in chromic acid for one minuteso that epoxy resin particles existing on the surface of the adhesivelayer 250 were dissolved and removed. As a result of the foregoingprocess, a coarsened surface 250 a in the form as shown in FIG. 8 (F)was formed on the surface of the adhesive layer 250. Then, the obtainedsubstrate was immersed in neutral solution (manufactured by Syplay),followed by cleaning the same with water.

(9) Then, as shown in FIG. 9 (G), an electroless copper plated film 251having a thickness of 0.6 μm was formed on the overall surface of thesubstrate.

(10) An etching resist was provided for the obtained substrate, andetching was performed by using sulfuric acid-hydrogen peroxide solution.Thus, an opening 251 a having a diameter of 50 μm was formed in aportion in which via hole can be formed, as shown in FIG. 9 (H).

(11) The surface of the opening 251 a is irradiated with a short pulse(10⁻⁴ second) laser beam (ML605GTL manufactured by Mitsubishi Electric).Thus, as shown in FIG. 9 (I), an opening 248 was formed in the adhesivelayer 250.

Then, a palladium catalyst (manufactured by Atotech) was attached to thesurface of the circuit board subjected to the coarsened process. Thus, acatalyst core was joined to each of the surface of the electrolessplated film 251 and the coarsened surface of the opening 248 for formingthe via hole.

(12) The obtained substrate was immersed in the electroless copperplating bath under the same conditions as those according to the firstembodiment. Thus, an electroless copper plated film 252 as shown in FIG.10 (J) and having a thickness of 1.6 μm was formed on the overall areaof the coarsened surface.

(13) Then, a commercial photosensitive dry film 254 was applied to theelectroless copper plated film 252, as shown in FIG. 10 (K). Then, amask film 255 having a pattern 255A printed thereon was placed. Thesubstrate was exposed to light with 100 mJ/cm², and then a developmentprocess was performed by using 0.8% sodium carbonate. Thus, a resist 254having a thickness of 15 μm was formed, as shown in FIG. 10 (L).

(14) The obtained substrate was electrolytic copper plated under thesame conditions as those according to the first embodiment. Thus, anelectrolytic copper plated film 256 having a thickness of 15 μm wasformed.

(15) The plating resist 254 was removed by using 5% KOH, and then mixedsolution of sulfuric acid and hydrogen peroxide was used to performetching so that the electroless copper plated film 252 under the platingresist 254 was dissolved and removed. Thus, a conductive circuit 258(including the via hole 260) formed as shown in FIG. 11 (N), composed ofthe electroless copper plated film 252 and the electrolytic copperplated film 25 and having a thickness of 18 μm was obtained.

Then, the substrate was immersed in 80 g/L chromic acid at 70° C. for 3minutes to etch the surface of the adhesive layer 250 for electrolessplating between the conductive circuits 258 by a depth opening 1 μm soas to remove the palladium catalyst on the surface. Thus, a multilayeredprinted circuit board structured as shown in FIG. 11 (N) wasmanufactured.

A first modification of the second embodiment will now be described withreference to FIGS. 12 and 13.

The processes (1) and (2) of the first embodiment were prevented so thata core substrate 230 having the lower conductive circuit shown in FIG. 7(B) and the surface which has been coarsened was manufactured. On theother hand, copper foil 229 having resin structured as shown in FIG. 12(A) was manufactured.

The copper foil 229 having resin was processed such that either side ofthe copper foil 232 having a thickness of 12 μm was etched similarly tothe process (2) of the second embodiment so as to be coarsened. Thus, acoarsened layer 232 a having a depth of 3 μm was formed. The coarsenedsurface was coated with epoxy resin 220, and then heated at 60° C. for 3hours. Thus, a B stage was obtained.

As shown in FIG. 12 (B), two copper foil 229 with resin were placed onthe two sides of the core substrate 230, followed by applying pressureof 10 kg/cm² at 150° C. so as to be integrated with each other. Thus, asubstrate structured as shown in FIG. 12 (C) was obtained. At this time,the epoxy-resin adhesive layer 220 of the copper foil having the resinas shown in FIG. 12 (A) was made contact with the lower conductivecircuit 234 of the core substrate 230.

Then, the substrate 230 was processed similarly to the process (10) ofthe second embodiment so that a dry film was bonded to the surface ofthe copper foil 232. Then, exposure and development processes wereperformed by using an ultraviolet ray so that an etching resist wasprovided. Then, solution composed of sulfuric acid and hydrogen peroxidewas used to perform etching so as to remove the copper foil 232 in whichthe via hole would be formed. Thus, an opening 233 as shown in FIG. 13was formed. Thus, a coarsened surface 220 a obtained by transferring theshape of the coarsened layer 232 a of the copper foil 232 was exposedover the surface of the adhesive layer 220.

The coarsened surface was irradiated with the carbon-dioxide gas laserbeam similar to the process (11) of the second embodiment so that anopening having a diameter of 50 μm and arranged to use to form the viahole was formed. Then, an electroless plated film and an electrolyticplated film were formed on the surface of the laminated substrate underconditions similar to those in the processes (13) to 15). Then theelectroless plated film was dissolved and removed in accordance with thepattern. Thus, a multilayered printed circuit board composed of theelectroless copper plated film and the electrolytic copper plated filmwas manufactured.

Comparative Example 1

A similar process to that according to the second embodiment wasperformed except for the coarsened surface which was not provided forthe surface of the adhesive layer which was irradiated with the laserbeam so that a multilayered printed circuit board was manufactured.

Comparative Example 2

The coarsened layer was not formed on the surface of the copper foilhaving resin.

Heating Test and Heat Cycle Test

The circuit boards obtained in the second embodiment, the modificationof the second embodiment and comparative example 1 were subjected toheat cycle tests which were performed at −55° C. to 125° C. and in whichthe cycle was repeated 500 times. In the tests, change rates of theresistance of the via hole portion were measured. Whether or not theresin in the periphery of the opening was expanded was confirmed byusing an optical microscope. Results were shown in table shown in FIG.56.

The manufacturing method according to the second embodiment is able toprevent leaving of resin on the surface of the lower conductive circuitin the portion in which the via holes are connected to each other.Therefore, separation between the lower conductive circuit and the viahole conductor can be prevented even during the heat cycle. Thus,defective connection in the via hole portion can be prevented. Thus, amultilayered printed circuit board exhibiting reliably of connection canbe obtained.

Third Embodiment

A multilayered printed circuit board and a manufacturing method thereforaccording to a third embodiment of the present invention will now bedescribed. The method of manufacturing the multilayered printed circuitboard according to the third embodiment has the steps of (1) forming aconductive circuit; (2) forming an interlayer insulating resin layer onthe conductive circuit; (3) applying a laser beam to form an opening forforming a via hole in the interlayer insulating resin layer; and (4)forming another conductive circuit having a via hole on the interlayerinsulating resin layer, wherein a solution containing cupric complex andorganic acid is used to coarsen the surface of the conductive circuitbefore the process (2).

The multilayered printed circuit board obtained by the foregoingmanufacturing method incorporates the conductive circuit, the surface ofwhich is coarsened by the etching solution containing the cupric complexand the organic acid. Moreover, the interlayer insulating resin layer isformed on the conductive circuit. In addition, the opening frequencyforming the via hole is formed in the interlayer insulating resin layer.Moreover, a stripe pits and projections are formed on the inner wall ofthe opening.

According to the third embodiment, the surface of the conductive circuitis coarsened by using the etching solution containing the cupric complexand the organic acid. Thus, a complicated coarsened surface as shown inFIGS. 14 to 16 is formed on the surface of the conductive circuit. Thecoarsened surface exhibits excellent adhesiveness with the interlayerinsulating resin layer which is formed on the coarsened surface. Inaddition, the coarsened surface is arranged to be irradiated with alaser beam. Even after the laser beam is applied, the shape of thecoarsened surface is not changed, that is, the coarsened surface is notflattened. Therefore, after the interlayer insulating resin layer hasbeen formed on the conductive circuit, the laser beam is applied so thatthe opening for forming the via hole can be formed without flattening ofthe conductive circuit.

The coarsened surface formed by using the etching solution containingthe cupric complex and the organic acid is free from a large quantity ofresidual resin if the opening is formed by the laser beam. Therefore,expansion of the resin left owing to the heating process which breaksthe connection with the via hole can be prevented.

Since the laser beam can easily be reflected, the incident light andreflected light of the laser beam can be allowed to interfere with eachother. Thus, an advantage can be obtained in that the stripe pits andprojections can easily be formed on the inner wall of the opening forforming the via hole.

When the stripe pits and projections are formed on the inner wall of theopening, all of the surface with the metal which constitutes the viahole are made contact have the anchoring effect. Therefore, thereliability of the connection of the via holes can be improved.

Therefore, the multilayered printed circuit board according to the thirdembodiment exhibits excellent adhesiveness between the conductivecircuit including the via hole portion and the interlayer insulatingresin layer. Moreover, also excellent adhesiveness can be realizedbetween the conductive circuit and the via hole (the conductive circuit)formed on the conductive circuit.

FIG. 14 is a plan view schematically showing a coarsened surface of theconductive circuit formed by the coarsening process according to thethird embodiment. FIG. 15 is a vertical cross sectional view taken alongline A-A shown in FIG. 14. FIG. 16 is a vertical cross sectional viewshowing another portion. In the drawings, reference numeral 321represents an opening (hereinafter called an “anchor portion”) in whicha surface portion which has not been etched is left. Reference numeral322 represents a recess portion. Reference numeral 323 represents aridge formed between the recess portions 322.

When the coarsening method according to the third embodiment isemployed, a coarsened surface having a shape, for example, as shown inFIGS. 14 to 16 is formed. That is, the anchor portion 321 includes amultiplicity of portions each having an upper portion, the width ofwhich is larger than the width of the lower portion.

The inner wall of the opening for forming the via hole according to thethird embodiment has the stripe pits and projections, as shown in FIG.20.

It is preferable that the depth of the pits and projections in thedirection of the surface of the wall is 0.1 μm to 5 μm and the intervalsbetween pits and projections are 1 μm to 20 μm. If the dimensions do notsatisfy the foregoing requirements, the adhesiveness with the metalwhich constitutes the via hole deteriorates.

As shown in FIG. 21, a coarsened surface having an average roughness Raof about 0.05 μm to 5 μm is formed on the surfaces of the stripe pitsand projections. The reason for this lies in that the anchor effect isimproved and, therefore, the adhesiveness with the via hole can beimproved.

When the via hole is formed on the conductive circuit having thecoarsened surface, the anchor effect connection can be obtained from theanchor portion 321 of the coarsened surface. As a result, a via holeexhibiting excellent adhesiveness with the lower conductive circuit canbe formed. When the via hole is formed by plating, plating can beallowed to sufficiently adhere to the coarsened surface. Therefore, theplated layer can reliably be formed on the recess portion 322 and theanchor portion 321. As a result, a via hole exhibiting excellentadhesiveness with the lower conductive circuit can be formed.

When the opening is formed by using the laser beam, the quantity of theresidual resin can be reduced owing to the coarsened structure.Therefore, the reliability of the connection with the via hole can beimproved.

A method of coarsening the surface of the conductive circuit by usingthe etching solution containing cupric complex and organic acid will nowbe described.

The cupric complex is not limited particularly. It is preferable thatcupric complex of azole is employed. The cupric complex serves as anoxidizer for oxidizing metal copper or the like.

The azole may be diazole, triazole or tetra azole. Among the foregoingmaterials, it is preferable that any one of the following material isemployed: imidazole, 2-methyl imidazole, 2-ethyl imidazole,2-ethyl-4-methyl imidazole, 2-phenyl imidazole or 2-undecyl imidazole.It is preferable that the quantity of cupric complex of azole which mustbe added is 1 wt % to 15 wt %. The reason for this lies in thatsolubility and stability of the cupric complex can be improved.

The organic acid is as well as mixed with the cupric complex to dissolvecopper oxide. When cupric complex of azole is employed, it is preferablethat the organic acid is selected from a group consisting of formicacid, acetic acid, propionic acid, butyric acid, valerianic acid,capronic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid,succinic acid, glutaric acid, maleic acid, benzonic acid, glycollicacid, lactic acid, malic acid and sulfamic acid. It is preferable thatthe content of the organic acid is 0.1 wt % to 30 wt %. The reason forthis lies in that the solubility of the oxidizd copper must bemaintained and stability of the solubility must be kept.

To assist the dissolution of copper and oxidation of azole, halogenions, for example, fluorine ions chlorine ions or bromine ions, may beadded to the etching solution. The halogen ions can be supplied ashydrochloric acid, sodium chloride resist and the like. It is preferablethat the quantity of halogen ions which must be added is 0.01 wt % to 20wt %. In this case, a coarsened surface exhibiting excellentadhesiveness with the interlayer insulating resin layer can be formed.

The foregoing etching solution can be prepared by dissolving cupriccomplex, the organic acid and, if necessary halogen ions in water. As acommercial etching solution, for example, “Mech Etch Bond” manufacturedby Mech may be employed.

When the foregoing etching solution is used to coarsen the conductivecircuit, the etching solution is sprayed to the surface of theconductive circuit (hereinafter called a “spraying method”). As analternative to this, the conductive circuit is immersed in the etchingsolution under a bubbling condition (hereinafter called a “bubblingmethod”). As a result of the foregoing process, oxygen coexists in theetching solution. Chemical reactions expressed by the following formulas(1) and (2) occur so that etching proceeds.

where A is a complexing agent (serving as a chelate agent) and n is thecoordination number.

As expressed by the foregoing chemical formulas, the prepared cuprouscomplex is dissolved owing to the action of the acid and oxidized withoxygen so as to be cupric complex so as to again contribute to theoxidation of copper.

It is preferable that the etching using the foregoing etching solutionis performed such that the depth of the etched portion is about 1 μm to10 μm. If the etching is performed excessively, defective connectionoccurs between the formed coarsened surface and the via hole conductor.

The coarsening process of the surface of the conductive circuit isperformed by the foregoing method, and then an interlayer insulatingresin layer is formed on the conductive circuit.

It is preferable that the interlayer insulating resin layer which isformed in the third embodiment is composed of thermosetting resin,thermoplastic resin or their composite resin.

It is preferable that the foregoing thermosetting resin is selected froma group consisting of thermosetting or thermoplastic polyolefine resin,epoxy resin, polyimide resin, phenol resin and bis maleimide-triazineresin.

It is preferable that the thermoplastic resin may be any one of thefollowing engineering plastic materials: polymethylpentenne (PMP),polystyrene (PS), polyethersulfone (PES), polyphenylene ether (PPF) andpolyphenylene sulfide (PPS).

In the third embodiment, it is preferable that the interlayer insulatingresin layer is made of the thermosetting or thermoplastic polyolefineresin.

The thermosetting or thermoplastic polyolefine resin may be, forexample, polyethylene, polypropylene, isobutylene, polybutadiene,polyisoprene or their copolymer.

As a commercial product of the polyolefine resin, it is exemplified by1592 which is a trade name of Sumitomo 3M. Commercial thermoplasticpolyolefine resin having a melting point of 200° C. is exemplified byTPX (melting point: 240° C.) which is a trade name of MitsuiPetrochemical and SPS (melting point: 270° C.) which is a trade name ofIdemitus Petrochemical.

The interlayer insulating resin layer is formed by applying non-hardenedsolution or by thermally pressing film-shape resin and by laminating thelayers.

Then, the interlayer insulating resin layer is irradiated with a laserbeam so that an opening for forming the via hole is formed. As the laserbeam for use in the foregoing operation, for example, a carbon-dioxidegas (CO2) laser beam, an ultraviolet laser beam and eximer laser beamare exemplified. Among the foregoing laser beams, it is preferable thatshort-pulse carbon-dioxide gas laser beam is employed. The short-pulsecarbon-dioxide gas laser beam is free from a large quantity of residualresin in the opening. Moreover, resin in the periphery of the opening isnot considerably damaged.

It is preferable that the intervals of the carbon-dioxide gas laser beampulses are 10⁻⁴ seconds to 10⁻⁸ seconds. It is preferable that time forwhich the laser beam is applied to form the opening is 10 μs to 500 μs.

It is preferable that the diameter of the beam is 1 mm to 20 mm and thelaser beam is applied one to ten shots in a multi-mode (a so-called“top-hat mode”). The multi-mode is able to uniform energy density of thesurface which is irradiated with the laser beam. Although a largeaperture cannot be obtained, an opening for forming a via hole similarto a complete round and free from considerable residues of resin.

To make the shape of the laser spot to be a complete round, the laserbeam is allowed to pass through an opening called a mask and formed intoa complete round. It is preferable that the diameter of the opening isabout 0.1 mm to about 2 mm.

When the opening is formed by the carbon-dioxide gas laser beam, it ispreferable that a desmear process is performed.

The desmear process can be performed by using an oxidizer in the form ofsolution of chromic acid or permanganate. The process may be performedby using oxygen plasma or mixture plasma of CF4 and oxygen or byperforming corona discharge. A low-pressure mercury lamp may be employedto apply ultraviolet rays to modify the surface.

Then, the electroless plating and electric plating to be described laterare performed so that an upper conductive circuit having the via hole isformed on the conductive circuit.

An example of a method of manufacturing a multilayered printed circuitboard according to the third embodiment will now be described.

(1) Initially, a circuit board having a lower conductive circuit formedon the surface of a resin substrate is manufactured. It is preferablethat the resin substrate is a resin substrate containing resin fibers.The resin substrate is exemplified by a glass-cloth epoxy resinsubstrate, a glass-cloth polyimide substrate, a glass-cloth bismaleimide-triazine resin substrate and a glass-cloth fluororesinsubstrate.

As an alternative to this, a copper-plated laminated board obtained bybonding copper foil on each of the two sides of the resin substrate maybe employed.

Usually, a through hole is formed in the resin substrate by drilling,and then the surface of the wall of the through hole and the surface ofthe copper foil are electroless-plated so that a through hole is formed.It is preferable that the electroless plating is copper plating. To formthick copper foil, electric plating may be performed. It is preferablethat the electric plating is copper plating.

Then, a process may be employed in which the inner wall of the throughhole and so forth are subjected to a coarsening process. Then, thethrough hole is filled with resin paste or the like, followed by forminga conductive layer for forming the surface by electroless plating orelectric plating.

After the foregoing process has been completed, a photolithographymethod is employed to form an etching resist on a copper solid patternformed on the overall surface of the substrate. Then, etching isperformed so that the lower conductive circuit is formed.

(2) Then, the lower conductive circuit is subjected to a coarseningprocess. That is, etching solution containing cupric complex and organicacid is used to form a coarsened surface on the lower conductive circuitby the spraying method or the bubbling method.

(3) Then, the interlayer insulating resin layer made of the foregoingpolyolefine resin and so forth is formed on each of the two sides of thecircuit substrate having the lower conductive circuit manufactured inthe process (2) by applying non-hardened solution or by thermallypressing film-shape resin and by laminating the layers. To establish theelectric connection with the lower conductive circuit, an opening forforming the via hole is formed in the formed interlayer insulating resinlayer by applying a laser beam.

(4) Then, the interlayer insulating resin layer is subjected to a plasmaprocess or a process using acid or the like so that the surface of theinterlayer insulating resin layer is coarsened.

When the plasma process has been performed, an intermediate layer may beformed which is composed of a metal material, such as Ni, Ti or Pd,which exhibits excellent adhesiveness with the interlayer insulatingresin layer in order to maintain the adhesiveness between the conductivecircuit, which is the upper layer, and the interlayer insulating resinlayer. It is preferable that the intermediate layer made of metal isformed by physical vaporization method (PVD), such as sputtering. It ispreferable that the thickness of the intermediate layer is about 0.1 μmto about 2.0 μm.

(5) The substrate subjected to the process (4) is electroless-plated.

As the electroless plating, copper plating is an optimum plating. It ispreferable that the thickness of electroless plating is 0.1 μm to 5 μm.The reason why the foregoing thickness is employed is that the functionas a conductive layer for electric plating which is performed later mustbe maintained and removal by etching must be permitted. The electrolessplating is not always required. The electroless plating may be omitted.

(6) A plating resist is formed on the electroless plated film formed inthe process (5). The plating resist is formed by laminating aphotosensitive dry film and by performing exposure and developmentprocesses.

(7) Then, electric plating is performed by using the electroless platedfilm or the like as the lead so that the conductive circuit isthickened. It is preferable that the thickness of the electricallyplated film is 5 μm to 30 μm.

At this time, the opening for forming the via hole may be charged toform a filled via structure.

(8) After the electrically plated film has been formed, the platingresist is separated. Then, the electroless plated film existing belowthe plating resist and the foregoing intermediate layer are removed byetching so that independent conductive circuits are realized. Theforegoing electric plating may be copper plating.

The etching solution is exemplified by persulfate solution, such assulfuric acid-hydrogen peroxide solution, ammonium persulfate, sodiumpersulfate or potassium persulfate; solution of ferric chloride orcupric chloride, hydrochloric acid; nitric acid; and hot dilute sulfuricacid. Etching solution containing the foregoing cupric complex andorganic acid may be employed to form a coarsened surface simultaneouslywith etching between the conductive circuits.

(9) Then, similarly to the process (2), the etching solution containingthe cupric complex and the organic acid is used to form the coarsenedsurface on the upper conductive circuit by the spraying method or thebubbling method.

(11) The processes (3) to (9) are repeated so that the upper conductivecircuit is formed. Thus, for example, a multilayered printed circuitboard formed into a 6-layered structure such that each side has threelayers is obtained.

Referring to the drawings, a method of manufacturing the multilayeredprinted circuit board according to the third embodiment will now bedescribed.

(1) A copper-plated laminated board is used as a start material (seeFIG. 17 (A)) incorporating a substrate 330 having a thickness of 1 mmand made of glass epoxy resin or BT (bis maleimide-triazine) resin andcopper foil 332 having a thickness of 18μm laminated on the two sides ofthe substrate 330. Initially, an opening is formed in the copper-platedlaminated board by drilling, followed by forming a plating resist. Then,the substrate is subjected to an electroless copper plating process sothat a through hole 336 is formed. Then, the copper foil is etched inaccordance with the pattern by a usual method so that an inner-layercopper pattern (the lower conductive circuit) 334 was formed on each ofthe two sides of the substrate.

(2) The substrate having the lower conductive circuit 334 was cleanedwith water, followed by drying the substrate. Then, etching solution wassprayed to the two sides of the substrate to etch the surface of thelower conductive circuit 334, the surface of the land of the throughhole 336 and the inner wall. Thus, a coarsened surface 338 was formed onthe overall surface of the lower conductive circuit 334 (see FIG. 17(B)). The etching solution was a mixture of 10 parts by weight ofimidazole copper (II) complex, 7 parts by weight of glycollic acid, 5parts by weight of potassium chloride and 78 parts by weight of ionexchange water.

(3) A resin filler 340 mainly composed of epoxy resin was applied to thetwo sides of the substrate by operating a printer so as to be enclosedbetween the lower conductive circuits 334 or in the through hole 336.Then, the substrate was heated and dried. That is, the foregoing processcauses the resin filler 340 to be enclosed between the lower conductivecircuits 334 or in the through hole 336 (see FIG. 17 (C)).

(4) Either side of the substrate subjected to the process (3) wasbelt-sander-polished by using belt sander paper (manufactured by Sankyo)in such a manner that leaving the resin filler 340 can be prevented onthe surface of the lower conductive circuit 334 and the surface of theland of the through hole 336. Then, flaws caused from thebelt-sander-polishing were removed by performing buff polishing. Theforegoing sequential polishing process is performed for another surface.The enclosed resin filler 340 was heated and hardened (see FIG. 17 (D)).

(5) The etching solution which is the same as that used in the process(2) was sprayed to the two sides of the substrate subjected to theprocess (4). The surface of the lower conductive circuit 334 which hasbeen temporarily flattened and the surface of the land of the throughhole 336 were etched. Thus, a coarsened surface 342 was formed on theoverall surface of the lower conductive circuit 334 (see FIG. 18 (A)).Then, the coarsened surface 342 was tin-substituted so that a Sn layerhaving a thickness of 0.3 μm was formed on the surface. Note that the Snlayer is omitted from illustration.

(6) Then, a thermosetting resin polyolefine resin sheet (1592 trade nameof Sumitomo 3M) having a thickness of 50 μm was laminated to each of thetwo sides of the substrate subjected to the foregoing process by heatingand pressing the sheet with pressure of 10 kg/cm² while the temperaturewas being raised to 50° C. to 180° C. Thus, an interlayer insulatingresin layer 350 made of polyolefine resin was formed (see FIG. 18 (B)).

(7) Then, CO2 gas laser having a wavelength of 10.4 μm was used to forman opening 348 having a diameter of 80 μm and arranged to form the viahole in the interlayer insulating resin layer 350 made of thepolyolefine resin under conditions that the diameter of the laser beamwas 5 mm, the mode was the top-hat mode, the pulse width was 50 μs, thediameter of the opening of the mask was 0.5 mm and the number of shotswas three (see FIG. 18 (C)). Then, oxygen plasma was used to perform adesmear process.

(8) Then, SV-4540 manufactured by Nihon Vacuum was used to perform aplasma process to coarsen the surface of the interlayer insulating resinlayer 350 (see FIG. 18 (D)). In the foregoing process, inert gas wasargon gas to perform the plasma process for two minutes under conditionsthat the electric power was 200 W, the pressure of the gas was 0.6 Paand the temperature was 70° C.

(9) Then, the same apparatus was operated to exchange internal argongas. Then, sputtering was performed by using Ni as a target underconditions that the atmospheric pressure was 0.6 Pa, the temperature was80° C., the electric power was 200 W and time was 5 minutes. Thus, a Nimetal layer 351 was formed on the interlayer insulating resin layer 350made of polyolefine resin. The thickness of the formed Ni metal layer351 was 0.1 μm. A copper metal layer 352 having a thickness of 0.1 μmwas, by sputtering, formed on the Ni metal layer 351 under similarconditions.

(10) The substrate having the metal layer 351 and the metal intermediatelayer 352 formed in the process (9) was electroless-plated under similarconditions to those described in the process (1). Thus, an electrolessplated film 353 having a thickness of 0.7 μm was formed (see FIG. 19(A)). Since the Ni metal layer 351, the metal intermediate layer 352 andthe electroless plated film 253 cannot clearly be shown from FIG. 19(B), the three layers are shown as one layer to which reference numeral352 is given.

(11) A commercial photosensitive dry film was applied to each of the twosides of the substrate subjected to the foregoing process. Then, aphotomask film was placed to perform exposure with 100 mJ/cm², and thena development process was performed by using 0.8% sodium carbonate.Thus, the pattern of the resist 354 having a thickness of 15 μm wasformed (see FIG. 19 (B)).

(12) Then, electric plating was performed under the same conditions asthose of the first embodiment so that an electrically plated film 356having a thickness of 15 μm was formed. Note that the electricallyplated film 356 caused thickening of the portion which would be formedin a conductive circuit 358 in the following process and enclosure ofplating into the portion which would be formed into a via hole 360 to becompleted.

(13) Then, the substrate was immersed in electroless nickel bath whichis solution (90° C.) containing nickel chloride (30 g/l), sodiumhypochlorite (10 g/l), sodium citrate (10 g/l). Thus, a nickel film 357having a thickness of 1.2 μm was formed on the electrolytic copperplated film (see FIG. 19 (C)).

(14) The plating resist 3 was separated and removed by

5% NaCH, and then Ni metal layer 351, the intermediate metal layer 352and the electroless plated film 353 existing below the resist 3 weredissolved and removed by an etching process which used a mixturesolution of nitric acid, sulfuric acid and hydrogen peroxide. Thus, aconductive circuit 358 (including a via hole 360) constituted by theelectrolytic copper plated film 356 and so forth and having a thicknessof 16 μm was formed (see FIG. 19 (D)).

(15) Then, the processes (5) to (14) are repeated (not shown) so that amultilayered structure that each side has three layers was formed. Then,formation of a solder-resist layer having an opening, that of anickel-plated film and that of a gold-plated film was performed. Then, asolder bump was formed so that a multilayered printed circuit boardhaving a solder bump was obtained.

Heating Test and Heat Cycle Test

The obtained multilayered printed circuit board was subjected to aheating test set to 128° C. for 48 hours and a heat cycle test at −55°C. to 125° C. to perform cycles 1,000 times. After the tests wereperformed, separation between the interlayer insulating resin layer andthe lower conductive circuit and change in the resistance of the viahole portion were evaluated. Results are shown in a table shown in FIG.57.

A first modification of the third embodiment will now be described.

A process similar to that according to the third embodiment wasperformed except for a bubbling method employed in the processes (2) and(5) and a coarsened surface formed on the surface of the lowerconductive circuit 334 under the following conditions so that amultilayered printed circuit board was manufactured. The obtainedmultilayered printed circuit board was subjected to the heating test andthe heat cycle test. Results are shown in the table shown in FIG. 57.

When the coarsened layer was formed, the conductive circuit was immersedin the etching solution employed in the processes (2) and (5). Then, thecoarsening process was performed while air was being bubbled.

Comparative Example 3

A process similar to that according to the third embodiment wasperformed except for employment of a Cu—Ni—P plating method and acoarsened layer made of a Cu—Ni—P alloy and formed on the surface of thelower conductive circuit 334 in the processes (2) and (5) so that amulti layered printed circuit board was manufactured. The obtainedmultilayered printed circuit board was subjected to the heating test andthe heat cycle test. Results are shown in the table shown in FIG. 57.

When the coarsened layer was formed, the substrate was degreased with analkali material, followed by performing soft etching. Then, a processusing catalyst solution composed of palladium chloride and organic acidwas performed so that a Pd catalyst was imparted to activate thecatalyst.

Then, the substrate was electroless-plated by using electroless platingbath, the pH of which was 9, the bath being water solution of, forexample, copper sulfate (3.2×10⁻² mol/l), nickel sulfate (2.4×10⁻³mol/l), citric acid (5.2×10⁻² mol/l), sodium hypophosphite (2.7×10⁻¹mol/l), boric acid (5.0×10⁻¹ mol/l) and a surface active agent (Surfinol465 manufactured by Nissin Chemical Industry) (1.0 g/L). Thus, acoarsened layer made of Cu—Ni—P alloy was formed on the overall surfaceof the conductive circuit.

Comparative Example 4

A process similar to that according to the third embodiment wasperformed except for employment of a blackening and reducing process anda coarsened surface formed on the surface of the conductive circuit inthe processes (2) and (5) so that a multilayered printed circuit boardwas manufactured. The obtained multilayered printed circuit board wassubjected to the heating test and the heat cycle test. Results are shownin the table shown in FIG. 57.

When the coarsening process was performed by blackening and reducingprocess was performed such that solution containing NaOH (10 g/l),NaClO₂ (40 g/l) and Na₃PO₄ (6 g/l) was employed as an oxidizing bath (ablackening bath) and solution containing NaOH (10 g/l) and NaBH₄ (6 g/1)was employed as a reducing bath. Thus, a coarsened surface having adepth of 3 μm was formed.

Comparative Example 5

A process similar to that according to the third embodiment wasperformed except for employment of a soft etching method using mixedsolution of hydrogen peroxide and sulfuric acid as etching solution toform a coarsened surface on the surface of the conductive circuit in theprocesses (2) and (5) so that a multilayered printed circuit board wasmanufactured. The obtained multilayered printed circuit board wassubjected to the heating test and the heat cycle test. Results are shownin the table shown in FIG. 57.

Comparative Example 6

A process similar to that according to the third embodiment wasperformed except for the following conditions for forming the coarsenedsurface on the surface of the conductive circuit in the processes (2)and (5) so that a multilayered printed circuit board was manufactured.The obtained multilayered printed circuit board was subjected to theheating test and the heat cycle test. Results are shown in the tableshown in FIG. 57.

When the coarsening process was performed such that an alumina polishingmaterial (having an average particle size 5 μm) was used under pressureof 1 kg/mm². Thus, a coarsened surface having a depth of 2 μm to 6 μmwas formed.

As can be understood from the results shown in the foregoing table, themultilayered printed circuit board according to the third embodiment wasfree from a great change rate of the resistance between the conductivecircuit and the via hole even after the heating test and the heat cycletest. Thus, no separation between the conductive circuit and theinterlayer insulating resin layer was observed. On the other hand, themultilayered printed circuit board according to the comparative exampleencountered an excessively great rate of change of the resistance orseparation observed after the test.

As described above, according to the method of manufacturing themultilayered printed circuit board according to the third embodiment, amultilayered printed circuit board can be manufactured with whichsatisfactory adhesiveness is realized between the conductive circuit andthe interlayer insulating resin layer which is formed on the conductivecircuit and also satisfactory adhesiveness with the via hole which isformed on the conductive circuit is realized even after the opening forforming the via hole is formed in the interlayer insulating resin layerby the laser beam.

The multilayered printed circuit board according to the third embodimentexhibits excellent adhesiveness between the conductive circuit includingthe via hole portion and the interlayer insulating resin layer.Moreover, excellent adhesiveness can be realized between the conductivecircuit and the via hole which is formed on the conductive circuit.

Fourth Embodiment

A multilayered printed circuit board and a manufacturing method thereforaccording to a fourth embodiment of the present invention will now bedescribed.

The structure of a multilayered printed circuit board 10 according tothe fourth embodiment will now be described with reference to FIGS. 27and 28.

FIG. 27 is a cross sectional view showing the multilayered printedcircuit board 10 in a state in which the IC chip has not been mounted.FIG. 28 is a diagram showing a state in which an IC chip 90 has beenmounted on the multilayered printed circuit board 10 and joined to adaughter board 94.

As shown in FIG. 27, the multilayered printed circuit board 10incorporates a core substrate 30 in which a through hole 36 is formed.Moreover, a conductive circuit 34 is formed on each of the two sides ofthe core substrate 30. An interlayer insulating resin layer 50 having avia hole 60 and a conductive circuit 58 is formed on the core substrate30. An upper interlayer insulating resin layer 150 having a via hole 160and a conductive circuit 158 is formed on the interlayer insulatingresin layer 50.

As shown in FIG. 28, a solder bump 76U for establishing the connectionwith a land 92 of the IC chip 90 is disposed in an opening 71U of asolder-resist 70 on the upper surface of the multilayered printedcircuit board. A solder bump 76D for establishing the connection with aland 96 of a daughter board 94 is formed in an opening 71D in the lowersurface. The solder bump 76U is connected to a through hole 36 through avia hole 160 formed in an upper interlayer insulating resin layer 150and a via hole 160 formed in the upper interlayer insulating resin layer150. The solder bump 76D is connected to the through hole 36 through thevia hole 160 formed in the upper interlayer insulating resin layer 150and the via hole 60 formed in the interlayer insulating resin layer 50.

The via hole 60 is formed by forming a through hole 48 in the interlayerinsulating resin layer 50 and by depositing an electroless plated film52 and an electrolytic plated film 56 on the inner surface of thethrough hole 48. Since the fourth embodiment is arranged to form thethrough hole 48 by a carbon dioxide laser beam, a small diameter (60 μm)can be realized. Since the stripe pits and projections are formed on theside wall of the through hole 48 as described later owing tointerference of laser beams when the through hole 48 is formed by usingthe laser beam, the electroless plated film 52 can make hermetic contactwith the side wall. Thus, the reliability of the via hole can beimproved.

On the other hand, the solder bumps 76U and 76D are, through anickel-plated layer 72 and a gold-plated layer 74, formed in theconductive circuit 158 and the via hole 160 below the openings 71U and71D formed in the solder-resist 70. The openings 71U and 71D of thesolder-resist 70 are formed by laser beams. That is, the fourthembodiment is arranged such that the opening is formed in thesolder-resist 70 by the laser beam. Therefore, the material is notlimited to the photosensitive resin. Therefore, a variety of materialsexhibiting an excellent electric characteristic can be employed as thesolder resist. Since the stripe pits and projections are formed on theside walls of the through holes (openings) 71U and 71D by using theinterference of the laser beams when the openings are formed by thelaser beams, the nickel-plated layer 72 can be made to hermeticallycontact with the side walls. As a result, the reliability of theconnection of each of the solder bumps 76U and 76D can be improved.

A method of manufacturing the multilayered printed circuit boardaccording to the fourth embodiment will now be described with referenceto the drawings.

The schematic structure of a carbon dioxide gas laser unit for forming athrough hole in the interlayer insulating resin layer and the solderresist will now be described with reference to FIG. 34.

FIG. 34 schematically shows the structure of the laser unit for formingthe through hole in the multilayered printed circuit board according tothe fourth embodiment. The laser unit is ML505GT manufactured byMitsubishi Electric. As a CO2-laser emitting unit 180, ML5003Dmanufactured by Mitsubishi Electric when the through hole (60 μm) 48 isformed in the interlayer insulating resin layer and a through hole (133μm) 71U for connecting the IC chip is formed in the upper portion of thesolder resist. When the through hole (650 μm) 71D for connecting themother board is formed in the lower portion of the solder resist,ML5003D2 manufactured by Mitsubishi Electric is employed.

Light emitted from the laser emitting unit 180 is made incident on agalvano head 170 through a transferring mask 182 for making a focalpoint on the substrate to be clear. The galvano head 170 is composed ofa pair of galvano mirrors consisting of a galvano mirror 174X forscanning the laser beam into the direction X and a galvano mirror 174Yfor scanning the laser beam into the direction Y. The mirrors 174X and174Y are operated by control motors 172X and 172Y. In accordance with acontrol command issued from a control unit (not shown), the motors 172Xand 172Y adjust the angles of the mirrors 174X and 174Y. Moreover, themotors 172X and 172Y transmits, to the computer, a detection signalobtained from encoders included therein.

The laser beam is allowed to pass through the mirrors 174X and 174Y soas to be scanned into the direction X-Y, and then allowed to passthrough a f-θ lens 176. Then, the laser beam is impinged on aninterlayer insulating resin layer of the core substrate 30 to bedescribed later. Thus, an opening (a through hole) 48 for forming thevia hole is formed. Similarly, the openings (through holes) 71U and 71Dfor the solder bump are formed in the solder-resist 70. The coresubstrate 30 is placed on an X-Y table 190 which is capable of moving inthe direction X-Y.

Here, the explanation is made with respect to compositions of A. anadhesive for electroless plating, B. an interlayer resin insulatingagent C. a resin filling agent, and D. Solder Resist Composition used inthe manufacturing method of the multilayer printed wiring board inaccordance with the fourth embodiment.

A. Raw Material Composition Substance for Adjusting and Manufacturing anAdhesive for Electroless Plating (an Adhesive for an Upper Layer)

[Resin Composition Substance {circle around (1)}]

A resin composition substance is obtained by stirring and mixing 35weight parts of a resin liquid, 3.15 weight parts of a photosensitivemonomer (manufactured by TO-A GOSEI, Alonix M315), 0.5 weight part of anantifoaming agent (manufactured by SAN-NOPUKO, S-65) and 3.6 weightparts of NMP. In the resin liquid, 25% of a cresol novolak type epoxyresin (manufactured by NIHON KAYAKU, molecular weight 2500) and 80 wt %of an acrylic substance in concentration are dissolved to DMDG. Apolyhydric acrylic-system monomer (manufactured by NIHON KAYAKU, R604)can be used as a photosensitive monomer.

[Resin composition substance {circle around (2)}]

A resin composition substance is obtained by mixing 12 weight parts ofpolyether sulfone (PES), 7.2 weight parts of epoxy resin particles(manufactured by SANYO KASEI, polymer pole) having an average particlediameter of 1.0 μm, and 3.09 weight parts of epoxy resin particleshaving an average particle diameter of 0.5 μm, and then adding 30 weightparts of NMP to the mixed material and stirring and mixing thesematerials by a beads mill.

[Hardening Agent Composition Substance {circle around (3)}]

A hardening agent composition substance is obtained by stirring andmixing 2 weight parts of an imidazole hardening agent (manufactured bySHIKOKU KASEI, 2E4MZ-CN), 2 weight parts of an optical starting agent(manufactured by CHIBAGAIGI, Irugacure I-907), 0.2 weight part of aphotosensitizer (manufactured by NIHON KAYAKU, DETX-S), and 1.5 weightparts of NMP.

B. Raw Material Composition Substance for Adjusting and Manufacturing anInterlayer Resin Insulating Agent (an Adhesive for a Lower Layer)

[Resin Composition Substance {circle around (1)}]

A resin composition substance is obtained by stirring and mixing 35weight parts of a resin liquid, 4 weight parts of a photosensitivemonomer (manufactured by TO-A GOSEI, Alonix M315), 0.5 weight part of anantifoaming agent (manufactured by SAN-NOPUKO, S-65) and 3.6 weightparts of NMP. In the resin liquid, 25% of a cresol novolak type epoxyresin (manufactured by NIHON KAYAKU, molecular weight 2500) and 80 wt %of an acrylic substance in concentration are dissolved to DMDG.

[Resin Composition Substance {circle around (2)}]

A resin composition substance is obtained by mixing 12 weight parts ofpolyether sulfone (PES) and 14.49 weight parts of epoxy resin particles(manufactured by SANYO KASEI, polymer pole) having an average particlediameter of 0.5 μm, and then adding 30 weight parts of NMP to the mixedmaterial and stirring and mixing these materials by a beads mill.

[Hardening Agent Composition Substance {circle around (3)}]

A hardening agent composition substance is obtained by stirring andmixing 2 weight parts of an imidazole hardening agent (manufactured bySHIKOKU KASEI, 2E4MZ-CN), 2 weight parts of an optical starting agent(manufactured by CHIBAGAIGI, Irugacure I-907), 0.2 weight part of aphotosensitizer (manufactured by NIHON KAYAKU, DETX-S), and 1.5 weightparts of NMP.

C. Raw Material Composition Substance for Adjusting and Manufacturing aResin Filling Agent

Use same as the composition substance according to the secondembodiment.

D. Raw Material Composition Substance for Adjusting and ManufacturingSolder Resist Composition

Solder resist composition is obtained by mixing 46.67 g ofphotosensitive oligomer (molecular weight 4000) obtained byacrylic-modifying 50% of epoxy groups of 60 percentage by weight ofcresol novolac dissolved into DMDG of 50% epoxy resin (Nippon Kayaku);15.0 g of 80 percentage by weight of bisphenol A type epoxy resin (YukaShell, Epikote 1001) dissolved into methyl ethyl ketone; 1.6 g ofimidazole hardener (Shikoku Chemicals, 2E4MZ-CN); 3 g of multivalentacrylic monomer (Nippon Kayaku, R604) which is photoreceptive monomer;1.5 g of the same multivalent acrylic monomer (KYOEISHA CHEMICAL,DPE6A); 0.71 g of a scattering anti-foaming agent (SANNOPCO, S-65); thenadding 2 g of benzophenone (KANTO CHEMICAL) used as a photo-initiator;and 0.2 g of Michler's ketone (KANTO CHEMICAL) used as a photosensitizerto the mixture and adjusting the viscosity to 2.0 Pa·s at 25° C.

The viscosity is measured by B-type measurement (TOKYO measurement DVL-Btype). A rotator No. 4 was used in 60 rpm, and a rotator No. 3 was usedin 6 rpm.

Description of a process for manufacturing the multilayered printedcircuit board according to the fourth embodiment will be continued withreference to FIGS. 22 to 27. In the fourth embodiment, the multilayeredprinted circuit board is formed by a semi-additive method.

(1) As shown in FIG. 22 (A), a copper-plated laminated board 30A wasemployed as the start material, the copper-plated laminated board 30Aincorporating a substrate 30 having a thickness of 0.8 mm and made ofglass epoxy resin or BT (bis maleimide-triazine) resin. Copper foil 32having a thickness of 12 μm is laminated on the substrate 30. Initially,an opening is formed in the copper-plated laminated board 30A bydrilling, and then electroless plating is performed. Then, etching inaccordance with a pattern is performed so that the through hole 36 andthe conductive circuit 34 are formed. Thus, a core substrate 30 shown inFIG. 22 (B) is formed.

(2) The substrate 30 having a plane layer 34 and a through hole 36 havebeen formed was cleaned with water, and then dried. Then, the oxidizingand reducing process was performed by using an oxidizing bath composedof NaOH (10 g/l), NaClO₂ (40 g/l) and Na₃PO₄ (6 g/l) and a reducing bathcomposed of NaOH (10 g/l) and NaBH₄ (6 g/l) so that a coarsened layer 38was formed on the surface of each of the inner-layer copper pattern 34and the through hole 36 (see FIG. 22 (C)).

(3) The raw material composition for preparing the resin filler shown inFIG. 22 (C) was mixed and kneaded so that the resin filler was obtained.

(4) The resin filler 40 obtained in the process (3) was applied to thetwo sides of the substrate 30 by using a roll coater within 24 hoursafter preparation of the resin filler 40. Thus, the resin filler 40 wasenclosed between the conductive circuits 34 and in the through hole 36.Then, the resin filler 40 was dried at 70° C. for 20 minutes. Anotherside is similarly processed. Thus, the resin filler 40 was enclosedbetween the conductive circuits 34 or in the through hole 36, and thenheated and dried at 70° C. for 20 minutes (see FIG. 22 (D)).

(5) Either side of the substrate 30 subjected to the process (4) wasbelt-sander-polished by using #600 belt polishing paper (manufactured bySankyo). Thus, polishing was performed such that the resin filler 40 wasnot left on the surface of the conductive circuit 34 and the surfaces oflands 36 a of the through hole 36. Then, flaws caused from thebelt-sander-polishing were removed by performing buff polishing. Theforegoing sequential polishing process was performed for another surface(see FIG. 23 (E)).

Then, heat treatment was performed at 100° C. for 1 hour, 120° C. for 3hours, 150° C. for 1 hour and 180° C. for 7 hours. Thus, the resinfiller 40 was hardened.

The surface layer portion of the resin filler 40 enclosed into thethrough hole 36 and so forth and the coarsened layer 38 on the uppersurface of the conductive circuit 34 are removed so that the two sidesof the core substrate 30 were flattened. Then, the resin filler 40 andthe side surface of the conductive circuit 34 were strongly brought intocontact with each other through the coarsened layer 38. The surface ofthe inner wall of the through hole 36 and the resin filler 40 arebrought into strong contact with each other through the coarsened layer38. Thus, the circuit board was obtained. As a result of the foregoingprocess, the surface of the resin filler 40 and that of the conductivecircuit 34 are made to be flush with each other.

(6) The substrate 30 having the conductive circuit 34 was degreased byusing alkali material, and soft etching was performed. Then, a processusing a catalyst composed of palladium chloride and organic acid wasperformed so that a Pd catalyst was imparted. Then, the catalyst wasactivated, and then the substrate was immersed in electroless platingsolution having PH=9 and composed of 3.2×10⁻² mol/l copper sulfate,3.9×10⁻³ mol/l nickel sulfate, 5.4×10⁻² mol/l complexing agent, 3.3×10⁻¹mol/l sodium hypophosphite, 5.0×10⁻¹ mol/l boric acid and a surfaceactive agent (Surfil 465 manufactured by Nissin Chemical Industry).After a lapse of one minute from the immersion, the substrate wasvertically and laterally vibrated one time at intervals of four seconds.Thus, a coating layer made of a needle alloy composed of Cu—Ni—P and acoarsened layer 42 were formed on the surface of the conductive circuit34 and the land 36 a of the through hole 36 (see FIG. 23 (F)).

Then, 0.1 mol/l tin borofluoride and 1.0 mol/l thiourea were used at atemperature of 35° C. and PH=1.2 so that Cu—Sn substitution reactionswere performed. Thus, a Sn layer (not shown) having a thickness of 0.3μm was formed on the surface of the coarsened layer.

(7) The raw material composition for preparing interlayer resininsulating material B was stirred and mixed to adjust the viscosity tobe 1.5 Pa·s so that the interlayer resin insulating material (for thelower layer) was obtained.

Then, the raw material composition for preparing interlayer resininsulating material A was stirred and mixed to adjust the viscosity tobe 7 Pa·s so that the interlayer resin insulating material (for theupper layer) was obtained.

(8) The interlayer resin insulating material (for the lower layer) 44obtained in the process (7) and having the viscosity of 1.5 Pa·s wasapplied to the two sides of the substrate obtained in the process (6) byusing a roll coater within 24 hours from the preparation. The substratewas allowed to stand in a horizontal state for 20 minutes, and then, thesubstrate was dried (pre-baked) at 60° C. for 30 minutes. Then, thephotosensitive adhesive-agent solution (for the upper layer) 46 obtainedin the process (7) and having the viscosity of 7 Pa·s was applied within24 hours after the preparation. Then, the substrate was allowed to standfor 20 minutes in a horizontal state, and then the substrate was dried(dry to touch) at 60° C. for 30 minutes. Thus, an adhesive-materiallayer 50α having a thickness of 35 μm was formed (see FIG. 23 (G)).

(9) A PET film 51 was brought into hermetic contact with each of the twosides of the substrate 30 having the adhesive-agent layer (see FIG. 24(H)). Then, exposure was performed by operating an extra high tensionmercury lamp with 500 mJ/cm². Then, the substrate 30 was exposed to theextra high tension mercury lamp with 3000 mJ/cm². Then, heating wasperformed at 100° C. for 1 hour, 120° C. for 1 hour and 150° C. for 3hours (post-baking). Thus, an interlayer insulating resin layer(two-layer structure) 50 having a thickness of 35 μm was manufactured.Then, the PET film 51 was separated.

(10) Then, the substrate 30 having the interlayer insulating resin layer50 was placed on the X-Y table 190 described with reference to FIG. 34.Then, the carbon-dioxide gas laser beam was applied so that the throughhole 48 was formed (see FIG. 24 (I)). Note that the tin-plated layer(not shown) was partially exposed to the through hole 48 which would beformed into the via hole.

To form the through hole having a diameter of 60 μm, ML5003D wasemployed as the laser oscillator of the laser unit. The irradiation wasperformed such that the energy of one pulse was 0.3 mJ, the pulse widthwas 50 μsec, the diameter of the mask was 0.5 mm, the pulse mode was aburst and multi-mode, the wavelength was 10.6 μm and the number of shotswas three.

FIG. 29 is an enlarged view of the portion C shown in FIG. 24 (I). Themultilayered printed circuit board according to the fourth embodiment isarranged such that the carbon-dioxide gas laser beam is verticallyapplied to the conductive circuit 34 below the interlayer insulatingresin layer 50 to cause the reflected wave and incident wave from theconductive circuit to interfere with each other. Thus, the stripe pitsand projections 49 are formed on the side wall 48 a of the through hole48 by electroless plating 49. That is, a portion in which the widths ofthe waves superimpose with each other are created for each halfwavelength (5 μm) of the carbon-dioxide gas laser beam. In the foregoingportion, relatively great heat is produced, causing the side wall 48 ato be annually scooped out. The depth D of the scooped portion is about0.1 μm to about 5 μm.

FIGS. 30 (A) and 30 (B) show sketches of the through hole 48 formed inthe interlayer insulating resin layer 50 by the carbon-dioxide gas laserbeam. FIG. 30 (A) shows a state in which the through hole is viewed froma diagonally upper position, while FIG. 30 (B) shows a state in whichthe through hole is viewed from a position directly above the throughhole.

It is preferable that the Interlayer insulating resin layer is made ofthermosetting resin or a composite material of the thermosetting resinand thermoplastic resin. The reason for this lies in that the stripepits and projections can easily be formed by the interference of thelaser beams. It is preferable that the thermosetting resin or thecomposite material of the thermosetting resin and the thermoplasticresin contains acrylic monomer. When the acrylic monomer is contained,plasma formation can easily be performed. Thus, occurrence of residuesof the resin in the through hole can be prevented.

(11) Then, the substrate 30 having the through hole 48 therein wasimmersed in chromic acid for 19 minutes to dissolve and remove epoxyresin particles existing on the surface of the interlayer insulatingresin layer 50. Thus, the surface of the interlayer insulating resinlayer 50 was coarsened (see FIG. 24 (J)). Then, the substrate wasimmersed in neutral solution (manufactured by Sypray), and then thesubstrate was cleaned with water.

(12) A palladium catalyst (manufactured by Atotech) was attached to thesurface of the substrate 30, the surface of which has been coarsened inthe process (10) so that catalyst cores are attached to the surface ofthe interlayer insulating resin layer 50. Then, the substrate 30 isimmersed in electroless copper plating solution under similar conditionsto those of the first embodiment. Thus, an electroless plated film 52having a thickness of 0.6 μm is formed on the overall surface (see FIG.24 (K)).

In the fourth embodiment, the stripe pits and projections are formed onthe side wall 48 a of the through hole 48 of the interlayer insulatingresin layer 50 by using interference of the laser beams. Therefore, theelectroless plated film 52 can be brought into hermetic contact with theside wall 48 a.

(13) A commercial photosensitive dry film was applied to the electrolessplated film 52 formed in the process (11), and then a mask was placed.Then, exposure was performed with 100 mJ/cm², and development wasperformed by using 0.8% sodium carbonate. Thus, a plating resist 54having a thickness of 15 μm was formed (see FIG. 24 (L)).

(14) Then, a portion in which the resist was not formed waselectrolytic-copper-plated, under conditions similar to those of thefirst embodiment. Thus, an electrolytic plated film 56 having athickness of 15 μm was formed (see FIG. 25 (M)).

(15) The plating resist 54 was separated and removed by 5% KOH, and thenthe electroless plated film 52 below the plating resist was dissolvedand removed by performing an etching process using mixed solution ofsulfuric acid and hydrogen peroxide. Thus, a conductive circuit 58 and avia hole 60 composed of the electroless plated film 52 and theelectrolytic plated film 56 and having a thickness of 18 μm were formed(see FIG. 25 (N)).

(16) A process similar to the process (6) was performed so that acoarsened surface 62 made of Cu—Ni—P was formed on the surface of theconductive circuit 58 and that of the via hole 60. Then, the surface wasSn-substitute (see FIG. 25 (O)).

(17) The processes (7) to (16) were repeated so that the upperinterlayer insulating resin layer 150, the via hole 160 and theconductive circuit 158 are formed. Thus, the multilayered printedcircuit board is manufactured (see FIG. 25 (P)). The substitution of Snwas omitted in the process for forming the upper conductive circuit.Note that Rj was 3 μm

(18) Then, solder bumps are formed on the foregoing multilayered printedcircuit board. The solder-resist composition described in D is appliedto each of the two sides of the substrate 30 obtained in the process(16) such that the thickness of the solder-resist composition is 45 μm.Then, the substrate is dried (dry to touch) at 70° C. for 20 minutes and70° C. for 30 minutes. Then, the PET film was brought into hermeticcontact, and then exposed with ultraviolet rays of 1000 mJ/cm². Then,heat treatment is performed under conditions of 80° C. for one hour,100° C. for one hour, 120° C. for one hour and 150° C. for three hours.Then, the PET film was separated so that the solder-resist layer(thickness: 20 μm) 70 is formed (see FIG. 26 (Q)).

(19) Then, the substrate 30 having the solder-resist 70 was placed onthe X-Y table 190 of the laser unit described with reference to FIG. 34.Then, the carbon-dioxide gas laser beam was applied to the substrate 30so that the through holes (openings) 71U and 71D were formed (see FIG.26 (R)).

To form the through hole 71 having a diameter of 133 μm in the uppersurface (the surface which is connected to the IC chip), a laseroscillator ML5003D was employed in the laser unit (ML505GT) wasemployed. The irradiation was performed such that the energy of onepulse was 2.0 mJ, the pulse width was 50 μsec, the diameter of the maskwas 2.0 mm, the pulse mode was a burst and multi-mode, the wavelengthwas 10.6 μm and the number of shots were two.

FIG. 31 (A) is an enlarged view of the portion A shown in FIG. 26 (R),that is, the through hole 71U in the portion which is connected to theIC chip. The multilayered printed circuit board according to the fourthembodiment is arranged such that the carbon-dioxide gas laser beam isvertically applied to the conductive circuit 158 below the solder-resist70 to cause the reflected wave and incident wave from the conductivecircuit to interfere with each other. Thus, the stripe pits andprojections are formed on the side wall 71 a of the through hole 71U ina direction of the opening. That is, a portion in which the widths ofthe waves superimpose with each other are created for each halfwavelength (5 μm) of the carbon-dioxide gas laser beam. In the foregoingportion, relatively great heat is produced, causing the side wall 71 ato be annually scooped out. The depth D of the scooped portion is about0.1 μm to about 5 μm. As can be understood from the sketch of thephotograph, the intervals of pits and projections (the distance betweenprojections) are about 5.5 μm. Since the multi-mode laser beam, thediameter of which can be reduced, is applied in the fourth embodiment, athrough hole having a relatively small diameter (50 μm to 300 μm) forforming the bump for establishing the connection with the IC chip can beformed.

FIGS. 32 (A) and 32 (B) show sketches of an enlarged photograph of thethrough hole (upper) 71U formed in the solder-resist 70 by thecarbon-dioxide gas laser beam. FIG. 32 (A) shows a state in which thethrough hole is viewed from a diagonally upper position, while FIG. 32(B) shows a state in which the through hole is viewed from a positiondirectly above the through hole.

FIG. 31 (B) is an enlarged view of the portion B shown in FIG. 26 (R),that is, the lower (a portion which is connected to the mother board)through hole 71D. To form the through hole 71D having a diameter of 650μm in the lower surface, a laser oscillator ML5003D2 in the laser unit(ML505GT) was employed. The irradiation was performed such that theenergy of one pulse was 14 mJ, the pulse width was 16 μsec, the diameterof the mask was 10.0 mm, the pulse mode was a burst and single-mode, thewavelength was 10.6 μm and the number of shots were five.

The multilayered printed circuit board according to the fourthembodiment is arranged such that the carbon-dioxide gas laser beam isvertically applied to the conductive circuit 158 below the solder-resist70. Thus, the reflected wave and incident wave from the conductivecircuit are caused to interfere with each other. Therefore, the stripepits and projections (hereinafter called “interference fringes) areformed on the side wall 71 a of the through hole 71D owing to theinterference. The depth of the scooped portion of the interferencefringes is about 0.1 μm to about 5 μm. Since the laser beam in thesingle mode with which the diameter of the laser beam can be enlarged isemployed in the fourth embodiment, a through hole having a relativelylarge diameter (300 μm to 650 μm) for forming the connection bump withthe mother board can be formed.

FIGS. 33 (A), 33 (B) and 33 (C) show sketches of an enlarged photographof the through hole (lower) 71D formed in the solder-resist 70 by thecarbon-dioxide gas laser beam. FIG. 33 (A) shows a state in which thethrough hole is viewed from a position directly above the through hole,FIG. 33 (B) shows a state in which the side wall of the through hole isviewed from a side position and FIG. 33 (C) shows a state in which thethrough hole is viewed from a diagonally upper position.

In the fourth embodiment, the through hole is formed in thesolder-resist layer by the laser beam. Therefore, a variety of materialsmay be employed to manufacture the solder-resist. The conventionaltechnique uses photolithography to form the through hole. Therefore,only the photosensitive resin is permitted as the material for thesolder-resist. Since the laser beam is used in the fourth embodiment, avariety of materials having an excellent electric characteristic can beemployed to manufacture the solder-resist. Since the through hole can beformed by using the laser unit which is the same used to form theinterlayer insulating resin layer, the multilayered printed circuitboard can be manufactured at a low cost. It is preferable that thesolder-resist layer is made of the thermosetting resin or a compositematerial of the thermosetting resin and the thermoplastic resin. Thereason for this lies in that the stripe pits and projections can easilybe formed by using the interference of the laser beams.

(20) Next, the substrate 30 is dipped for 20 minutes into an electrolessnickel plating liquid of pH=4.5 constructed by nickel chloride 2.31×10⁻¹mol/l, sodium hypophosphite 2.8×10⁻¹ mol/l and sodium citrate 1.85×10⁻¹mol/l. Thus, a nickel plating layer 72 having 5 μm in thickness isformed in the opening portions 71U, 71D. Further, this substrate isdipped for 7 minutes and 20 seconds into an electroless gold platingliquid constructed by potassium gold cyanide 4.1×10⁻² mol/l, ammoniumchloride 1.87×10⁻¹ mol/l, sodium citrate 1.16×10⁻¹ mol/l and sodiumhypophosphite 1.7×10⁻¹ mol/l in a condition of 80° C. Thus, a goldplating layer 74 having 0.03 μm in thickness is formed on the nickelplating layer so that a soldering pad 75 is formed in the via hole 160and the conducting circuit 158 (refer FIG. 26 (S)).

(21) Then, solder paste, which is metal having a low melting point wasprinted to the openings 71U and 71D of the solder-resist 70, and thenreflowing was performed at 200° C. Thus, solder bumps (solder) 76U and76D were formed. As a result, the multilayered printed circuit board 10was manufactured (see FIG. 27). In the fourth embodiment, solder isenclosed through the nickel-plated layer 72 and the gold-plated layer 74to form the solder bumps 76U and 76D. Therefore, the nickel-plated layer72 and the gold-plated layer 74 are brought into hermetic contact withthe openings 71U and 71D each having the stripe pits and projections.Thus, the solder bumps 76U and 76D can strongly be connected to theconductive circuit 158.

Then, a pad 92 of the IC chip 90 is located to correspond to the solderbump 76U of the multilayered printed circuit board 10, followed byperforming reflowing. Thus, the IC chip 90 is mounted. The multilayeredprinted circuit board 10, on which the IC chip 90 has been mounted, isplaced to correspond to the bump 96 adjacent to the daughter board 94,followed by performing reflowing. Thus, multilayered printed circuitboard 10 is joined to the daughter board 94 (see FIG. 28).

The obtained printed circuit board was subjected to a heating test(heated at a temperature of 121° C. for 48 hours) to examine the changerate of the resistance of the via hole portion.

The IC chip was mounted so as to be subjected to a TS test (in thistest, the mounted IC chip was allowed to stand at −125° C. for 30minutes and 55° C. for 30 minutes). The test was repeated 1000 times toexamine the change rate of the resistance in the via hole portion.

To make a comparison, a printed circuit was subjected to a similar test,the printed circuit being a printed circuit board having thesolder-resist layer according to the embodiment and exposed toultraviolet rays and the through hole formed by performing developmentusing diethylene glycol dimethylether.

As a result, the printed circuit board according to the fourthembodiment resulted in a change rate of the resistance being 1% in bothof the heating test and the TS test.

On the other hand, the change rate of the comparative example was 5%.

As described above, the printed circuit board according to the fourthembodiment exhibits excellent reliability of the connection betweenprecise via holes.

The IC chip was mounted on the printed circuit board so as to besubjected to a HAST test (relative humidity was 100%, applied voltagewas 1.3 V and the board was allowed to stand at 121° C. for 48 hours).Moreover, cross cuts were examined by a fluorescent X-ray analyzer(Rigaku RIX2100) to confirm Pb dispersed in the solder-resist layer.

Moreover, the TS test (the sample was allowed to stand at −125° C. for30 minutes and 55° C. for 30 minutes) was repeated 1000 times to examineseparation of the Ni layer and the Au layer and occurrence of a crack inthe solder-resist layer.

To make a comparison, a printed circuit was subjected to a similar test,the printed circuit being a printed circuit board having thesolder-resist layer according to the embodiment and exposed toultraviolet rays and the through hole formed by performing developmentusing diethylene glycol dimethylether.

As a result, the printed circuit board according to the fourthembodiment was substantially free from migration of Pb.

On the other hand, the printed circuit board according to thecomparative example encountered migration of Pb in spite of preventionof a short circuit. In the TS test, the embodiment was free fromseparation and a crack. On the other hand, the comparative exampleencountered separation of the bump in each Ni layer and a crack of thesolder-resist layer. As described above, the printed circuit boardaccording to the fourth embodiment is able to prevent separation of theNi-plated film, dispersion of metal ions from the bump and a crack ofthe solder-resist layer.

Fifth Embodiment

A multilayered printed circuit board according to a fifth embodiment ofthe present invention will now be described.

First Modification

(1) A double-side copper-plated laminated board (R5715 manufactured byMatsushita Electric Works) 130A which incorporated a substrate 130 towhich copper foil 132 having a thickness of 12 μm was applied and havinga thickness of 0.6 mm was prepared (see FIG. 35 (A)).

(2) The copper foil 132 was etched by solution of sulfuric acid andhydrogen peroxide to make the thickness to be 5 μm (see FIG. 35 (B)).

(3) The double-side copper-plated laminated board 130A was irradiatedwith carbon-dioxide gas laser beam (ML605GTL manufactured by MitsubishiElectric) under pulse conditions of 30 mJ, 52×10⁻⁶ second and 10 shots.Thus, an opening 116 having a diameter of 150 μm (tapered such thatupper diameter D1: 160 μm and lower diameter D2: 140 μm) was formed (seeFIG. 35 (C)). Thus, the opening can be formed in the substrate 130through the copper foil 132 having the thickness of 5 μm by using thelaser beam.

(3) The inner surface of the opening 116 was electroless-plated so thata plated through hole 136 was formed (see FIG. 35 (D)).

Second Modification

(1) A double-side copper-plated laminated board (R5715 manufactured byMatsushita Electric Works) 230A which incorporated a substrate 230 towhich copper foil 232 having a thickness of 12 μm was applied and havinga thickness of 0.6 mm was prepared (see FIG. 36 (A)).

(2) The copper foil 232 was etched by solution of sulfuric acid andhydrogen peroxide to make the thickness to be 9 μm (see FIG. 36 (B)).

(3) The double-side copper-plated laminated board 230A was irradiatedwith carbon-dioxide gas laser beam (ML605GTL manufactured

by Mitsubishi Electric) under pulse conditions of 30 mJ, 52×10 ⁻⁶ secondand 15 shots. Thus, an opening 116 having a diameter of 150 μm (taperedsuch that upper diameter D1: 160 μm and lower diameter D2: 140 μm) wasformed (see FIG. 36 (C)). Thus, the opening can be formed in thesubstrate 130 through the copper foil 132 having the thickness of 9 μmby using the laser beam.

(4) Electroless plating was performed similarly to the firstmodification so that a plated through hole 236 was formed (see FIG. 36(D)).

Third Modification

(1) A double-side copper-plated laminated board (R5715 manufactured byMatsushita Electric Works) 330A which incorporated a substrate 330 towhich copper foil 332 having a thickness of 12 mm was applied and havinga thickness of 0.6 mm was prepared (see FIG. 37 (A)).

(2) The copper foil 332 was etched by solution of sulfuric acid andhydrogen peroxide to make the thickness to be 5 μm (see FIG. 37 (B)).

(3) The double-side copper-plated laminated board 330A was irradiatedwith carbon-dioxide gas laser beam (ML605GTL manufactured by MitsubishiElectric) under pulse conditions of 30 mJ, 52×10⁻⁶ second and 15 shots.Thus, an opening 316 having a diameter of 150 μm (tapered such thatmaximum upper diameter D3: 160 μm and minimum diameter D4: 140 μm) wasformed. The cross section of the opening 316 was a concave shape (seeFIG. 37 (C)).

(4) Electroless plating was performed similarly to the firstmodification so that a plated through hole 336 was formed (see FIG. 37(D)). In the fourth modification, the laser beams are applied from bothof the right side and reverse side. Therefore, the through hole can beformed if the thickness of the substrate is large.

Comparative Example 7

(1) A double-side copper-plated laminated board (R5715 manufactured byMatsushita ElectricWorks) to which copper foil having a thickness of 12μm was applied and which had a thickness of 0.6 mm was prepared.

(2) The double-side copper-plated laminated board was irradiated withcarbon-dioxide gas laser beam (ML605GTL manufactured by MitsubishiElectric) under pulse conditions of 30 mJ, 52×10⁻⁶ second and 15 shots.However, formation of an opening was impossible. Thus, formation of athrough hole cannot be performed if the thickness of the copper foil islarger than 12 μm.

Fourth Modification

The fourth embodiment for manufacturing a multilayered printed circuitboard by forming a through hole by using a laser beam will now bedescribed with reference to FIGS. 38 to 44.

The structure of a multilayered printed circuit board 10 according to afourth modification will now be described with reference to FIG. 43. Themultilayered printed circuit board 10 incorporates a core substrate 30having built-up circuit layers 80A and 80B formed on the right side andreverse side thereof. The built-up circuit layer 80A incorporates aninterlayer insulating resin layer 50 having a via hole 60 and aconductive circuit 58; and an upper interlayer insulating resin layer150 having a via hole 160 and a conductive circuit 158. The built-upcircuit layer 80B incorporates an interlayer insulating resin layer 50having the via hole 60 and the conductive circuit 58; and an upperinterlayer insulating resin layer 150 having the via hole 160 and theconductive circuit 158.

A solder bump 76U for establishing the connection with a land (notshown) of the IC chip is formed on the upper surface of the multilayeredprinted circuit board 10. The solder bump 76U is connected to thethrough hole 36 through the via hole 160 and the via hole 60. On theother hand, a solder bump 76D for establishing the connection with aland (not shown) of the daughter board is formed on the lower surface.The solder bump 76D is connected to the through hole 36 through the viahole 160 and the via hole 60. The description of the method ofmanufacturing the multilayered printed circuit board 10 will becontinued.

Manufacturing of Printed Circuit Board

(1) A copper-plated laminated board 30A having the core substrate 30which had a thickness of 0.6 mm, which was made of glass epoxy resin andto which copper foil 32 having a thickness of 12 μm was laminated toeach of the two sides thereof was employed as the start material (seeFIG. 38 (A)). Then, the copper-plated laminated board 30A was etched tohave the thickness to be 5 μm (see FIG. 38 (B)).

(2) The copper-plated laminated board 30A was irradiated with acarbon-dioxide gas laser beam (ML605GTL manufactured by MitsubishiElectric) under pulse conditions of 30 mJ, 52×10⁻⁶ second and 15 shots.However, formation of an opening was impossible. Thus, a through hole 16was formed which had a thickness of 100 μm (tapered such that upperdiameter D1:

110 μm and lower diameter D2: 90 μm) (see FIG. 38 (C)).

Then, electroless plating and electrolytic plating were performed (seeFIG. 38 (D)). Then, the copper foil was etched in accordance with apattern by a usual method so that an inner-layer copper pattern (thelower conductive circuit) 34 having a thickness of 15 μm and the throughhole 36 were formed on the two sides of the substrate (see FIG. 38 (E)).

Then, the coarsened surface 38 was formed on each of the surface of theinner-layer copper pattern 34, the surface of the land 36A of thethrough hole 36 and the inner wall. Thus, a printed circuit board wasmanufactured (see FIG. 38 (F)). The coarsened surface 38 was formed bycleaning the foregoing substrate 30 with water, followed by drying thesubstrate 30. Then, etching solution was sprayed to the two sides of thesubstrate to etch the surface of the inner-layer copper pattern 34, thesurface of the land 36 a of the through hole 36 and the inner wall. Theetching solution was a mixture of 10 parts by weight imidazole copper(II) complex, 7 parts by weight of glycollic acid, 5 parts by weight ofpotassium chloride and 78 parts by weight of ion exchange water.

(3) Then, resin layer 40 was formed between the inner-layer copperpatterns 34 and in the through hole 36 of the printed circuit board (seeFIG. 39 (G)). The resin layer 40 was formed by applying the resin fillerwhich was previously prepared and which was similar to that according tothe fourth embodiment to the two sides of the printed circuit board by aroll coater so as to be enclosed between the inner-layer copper patternsand in the through hole, followed by heating and hardening the resinfiller.

(4) Either side of the substrate 30 obtained in the process (3) wasbelt-sander-polished. The polishing operation was performed by using#600 belt sander paper (manufactured by Sankyo) such that leaving of theresin filler 40 on the coarsened layer 38 of the inner-layer copperpattern 34 and the surface of the land 36 a of the through hole 36 wasprevented (see FIG. 39 (H)). Then, flaws caused from thebelt-sander-polishing were removed by performing buff-polishing. Theforegoing sequential polishing operation was performed for another side.

(5) Then, the exposed inner-layer copper pattern 34 and the uppersurface of the land 36 a of the through hole 36 were coarsened byperforming an etching process in (2). Thus, a coarsened layer 42 havinga depth of 3 μm was formed (see FIG. 39 (I)).

The coarsened layer 42 was Sn-substituted so that an Sn layer (notshown) having a thickness of 0.3 μm was formed. The substitutionalplating was performed under conditions that 0.1 mol/l tin borofluorideand 1.0 mol/l thiourea were used, the temperature was 50° C. and pH was1.2. Thus, the coarsened surface was Cu—Sn-substituted.

(6) The two sides of the Obtained printed circuit board 30 were coatedwith the adhesive agent for electroless plating similar to that used inthe fourth embodiment by using a roll coater. The adhesive agent wasdried at 60° C. for 30 minutes after the substrate was allowed to standfor 20 minutes in a horizontal state. Thus, an adhesive-agent layer 50having a thickness of 35 μm was formed (see FIG. 39 (J)).

(7) The two sides of the obtained printed circuit board 30 were exposedwith 500 mJ/cm² by operating an extra high tension mercury lamp so as tobe heated at 150° C. for 5 hours.

(8) The obtained printed circuit board 30 was immersed in chromic acidfor one minute so that epoxy resin particles existing on the surface ofthe adhesive layer 50 were dissolved and removed. As a result of theforegoing process, a coarsened surface was formed on the surface of theadhesive layer 50. Then, the obtained substrate 30 was immersed inneutral solution (manufactured by Syplay), followed by cleaning the samewith water (see FIG. 39 (K)).

(9) Then, the overall surface of the substrate 30 was electroless-plated44 having a thickness of 0.6 mm (see FIG. 40 (L)).

(10) An etching resist (not shown) was provided for the obtainedsubstrate, and etching was performed by using sulfuric acid-hydrogenperoxide solution. Thus, an opening 44 a having a diameter of 50 μm wasformed in a portion of the electroless copper plating 44 in which viahole will be formed (see FIG. 40 (M)).

(11) The electroless copper plating 44 was used as a conformal mask toirradiate short-pulse (10⁻⁴ second) laser beam (ML605GTL manufactured byMitsubishi Electronics). Thus, the adhesive-agent layer 50 below theopening 44 a was removed so that an opening 48 for forming the via holewas formed (see FIG. 40 (N)).

Then, a palladium catalyst (manufactured by Atotech) was attached to thesurface of the circuit board 30 so that a catalyst core was added to thesurface of the electroless-plated film 44 and the coarsened surface ofthe opening 48 for forming the via hole.

(12) The obtained substrate 30 was immersed in the electroless copperplating bath. Thus, an electroless copper plated film 52 having athickness of 1.6 μm was formed on the overall surface of the substrate30 (see FIG. 40 (O)).

(13) Then, a commercial photosensitive dry film (not shown) was appliedto the electroless copper plated film 52. Then, a mask film (not shown)having a pattern printed thereon was placed. The substrate 30 wasexposed to light with 100 mJ/cm², and then a development process wasperformed by using 0.8% sodium carbonate. Thus, a resist 54 having athickness of 15 μm was formed (see FIG. 40 (P)).

(14) The obtained substrate was electrolytic copper plated so that anelectrolytic copper plated film 56 having a thickness of 15 μm wasformed (see FIG. 41 (Q)).

(15) The plating resist 54 was removed by using 5% KOH, and then mixedsolution of sulfuric acid and hydrogen peroxide was used to performetching so that the electroless copper plated film 52 below the platingresist was dissolved and removed. Thus, a conductive circuit 58 and thevia hole 60 composed of the copper foil 32, the electroless plating 44,the electroless plated film 52 and the electrolytic copper plated film56 and having a thickness of 18 μm (10 μm to 30 μm) were obtained (seeFIG. 41 (R)). The thickness was made to be 10 μm to 30 μm tosimultaneously realize a fine pitch and reliability of the connection.

Then, the substrate was immersed in 80 g/L chromic acid at 70° C. toetch the surface of the adhesive-agent layer 50 for the electrolessplating between the conductive circuits 58 by a depth opening 1 μm so asto remove the palladium catalyst on the surface.

(16) A process similar to the process (5) was performed so that acoarsened surface 62 made of Cu—Ni—P was formed on each of the surfaceof the conductive circuit 58 and that of the via hole 60. Then, thesurface was Sn-substituted (see FIG. 41 (S)).

(17) The processes (6) to (16) are repeated so that the upper interlayerinsulating resin layer 160, the via hole 160 and the conductive circuit158 are formed. Then, the coarsened layer 162 is formed on the surfaceof the via hole 160 and that of the conductive circuit 158. Thus, themultilayered printed circuit board is manufactured (see FIG. 40 (T).Note that the Sn substitution was not performed in the process forforming the upper conductive circuit.

(18) Then, a solder bump is formed on the above-mentioned multilayeredprinted circuit board. The two sides of the substrate 30 obtained in theprocess (17) are coated with a solder-resist composition similar to thataccording to the fourth embodiment, the thickness of the solder-resistlayer composition being 45 mm. Then, a drying process was performed at70° C. for 20 minutes and at 70° C. for 30 minutes. Then, a photomaskfilm (not shown) on which a circle pattern (a mask pattern) has beendrawn and which has a thickness of 5 mm was hermetically placed. Then,exposure is performed with ultraviolet rays with 1000 mJ/cm² so that aDMTG development process is performed. Then, heating is performed at 80°C. for one hour, 100° C. for one hour, 120° C. for one hour and 150° C.for three hours. Thus, a solder-resist layer (having a thickness of 20μm) 70 is formed which has an opening (having a diameter of 200 μm) 71in the solder pad portion (including the via hole and its land portion)(see FIG. 42 (U)).

(19) Then, the nickel-plated layer 72 was formed. Then, the gold-platedlayer 74 having a thickness of 0.03 μm is formed on the nickel-platedlayer so that the solder pad 75 is formed on the via hole 160 and theconductive circuit 158 (see FIG. 42 (V)).

(22) Solder paste was printed on an opening 71 of the solder-resistlayer 70, followed by performing reflowing at 200° C. Thus, solder bumps(solder) 76U and 76D were formed. As a result, the multilayered printedcircuit board 10 was formed (see FIG. 42 (W)).

Fifth Modification

The fifth modification is similarly to the fourth modification. Notethat a substrate 330 having a through hole was employed as the coresubstrate, the substrate 330 having a concave through hole 336 obtainedin the third modification.

Sixth Modification

FIG. 44 shows the structure of a multilayered printed circuit boardaccording to a sixth modification. The foregoing printed circuit boardhas the structure that the diameter D of the communication hole 16 ofthe through hole 36 formed by a laser beam is 100 mm to 200 mm. In thismodification, the communication hole 16 is not tapered. The multilayeredprinted circuit board 10 has the via hole 60 which is so formed as toclose the communication hole 16 of the through hole 36 formed in thecore substrate 30. Thus, the via hole 60 is formed at a positiondirectly above the through hole 36. Therefore, the length of the circuitin the multilayered printed circuit board can be minimized. Therefore,the operation speed of the IC chip can be raised.

The region directly above the through hole 36 is made to serve as theinner pad so that dead space is eliminated. Since a necessity of wiringthe inner pad for establishing the connection from the through hole 36to the via hole 60 can be eliminated, the shape of the land 36 a of thethrough hole 36 can be made to be true round. As a result, the densityat which the through holes 36 are formed in the multilayered coresubstrate 30 can be raised. If 20% to 50% of the surface of the bottomof the through hole 36 formed in the multilayered core substrate 30 ismade contact with the land 36 a of the through hole 36, satisfactoryelectric connection can be realized in this embodiment.

As described above, the fifth embodiment is able to form an operation inthe copper-plated laminated board by the carbon-dioxide gas laser beam.Therefore, a small through hole can be formed at a low cost.

Sixth Embodiment

A multilayered printed circuit board according to a sixth embodiment ofthe present invention will now be described.

Manufacturing of Printed Circuit Board

(1) A copper-plated laminated board 30A having the core substrate 30(R5715 (Tg: 190° C.) manufactured by Matsushita ElectricWorks) which hada thickness of 0.6 mm, which was made of glass epoxy resin and to whichcopper foil 32 having a thickness of 12 μm was laminated to each of thetwo sides thereof was employed as the start material (see FIG. 45 (A)).Then, the copper-plated laminated board 30A was etched to have thethickness to be 5 μm (see FIG. 45 (B)).

(2) The copper-plated laminated board 30A was irradiated with acarbon-dioxide gas laser beam (ML605GTL manufactured by MitsubishiElectric) under pulse conditions of 30 mJ, 52×10⁻⁶ second and 15 shots.Thus, a through hole 16 having a diameter D of 100 μm was formed (seeFIG. 45 (C)). The through hole 16 was not tapered.

Then, electroless plating and electrolytic plating were performed (seeFIG. 45 (D)). Then, the copper foil was etched in accordance with apattern by a usual method so that an inner-layer copper pattern (thelower conductive circuit) 34 having a thickness of 15 μm and the throughhole 36 were formed on the two sides of the substrate (see FIG. 45 (E)).

Then, the coarsened surface 38 was formed on each of the surface of theinner-layer copper pattern 34, the surface of the land 36A of thethrough hole 36 and the inner wall. Thus, a printed circuit board wasmanufactured (see FIG. 46 (F)). The coarsened surface 38 was formed bycleaning the foregoing substrate 30 with water, followed by drying thesubstrate 30. Then, etching solution was sprayed to the two sides of thesubstrate to etch the surface of the inner-layer copper pattern 34, thesurface of the land 36 a of the through hole 36 and the inner wall. Theetching solution was a mixture of 10 parts by weight imidazole copper(II) complex, 7 parts by weight of glycollic acid, 5 parts by weight ofpotassium chloride and 78 parts by weight of ion exchange water.

(3) Then, resin layer 40 was formed between the inner-layer copperpatterns 34 and in the through hole 36 of the printed circuit board (seeFIG. 46 (G)). The resin layer 40 was formed by applying the resin fillerwhich was previously prepared and which was similar to that according tothe fourth embodiment to the two sides of the printed circuit board by aroll coater so as to be enclosed between the inner-layer copper patternsand in the through hole, followed by heating and hardening the resinfiller at 100° C. for one hour, 120° C. for three hours, 150° C. for onehour and 180° C. for 7 hours.

(4) Either side of the substrate 30 obtained in the process (3) wasbelt-sander-polished. The polishing operation was performed by using#600 belt sander paper (manufactured by Sankyo) such that leaving of theresin filler 40 on the coarsened layer 38 of the inner-layer copperpattern 34 and the surface of the land 36 a of the through hole 36 wasprevented (see FIG. 46 (H)). Then, flaws caused from thebelt-sander-polishing were removed by performing buff-polishing. Theforegoing sequential polishing operation was performed for another side.

(5) Then, the exposed inner-layer copper pattern 34 and the uppersurface of the land 36 a of the through hole 36 were coarsened byperforming an etching process in (2). Thus, a coarsened layer 42 havinga depth of 3 μm was formed (see FIG. 46 (I)).

The coarsened layer 42 was Sn-substituted so that an Sn layer (notshown) having a thickness of 0.3 μm was formed. The substitutionalplating was performed under conditions that

0.1 mol/L tin borofluoride and 1.0 mol/L thiourea were used, thetemperature was 50° C. and pH was 1.2. Thus, the coarsened surface wasCu—Sn-substituted.

(6) The two sides of the obtained printed circuit board 30 were coatedwith the adhesive agent for electroless plating similar to that used inthe fourth embodiment by using a roll coater. The adhesive agent wasdried at 60° C. for 30 minutes after the substrate was allowed to standfor 20 minutes in a horizontal state. Thus, an adhesive-agent layer 50having a thickness of 35 μm was formed (see FIG. 46 (J)).

(7) The two sides of the obtained printed circuit board 30 were exposedwith 500 mJ/cm² by operating an extra high tension mercury lamp so as tobe heated at 150° C. for 5 hours.

(8) The obtained printed circuit board 30 was immersed in chromic acidfor one minute so that epoxy resin particles existing on the surface ofthe adhesive layer 50 were dissolved and removed. As a result of theforegoing process, a coarsened surface was formed on the surface of theadhesive layer 50. Then, the obtained substrate 30 was immersed inneutral solution (manufactured by Syplay), followed by cleaning the samewith water (see FIG. 46 (K)).

(9) Then, the overall surface of the substrate 30 was electroless-plated44 having a thickness of 0.6 μm (see FIG. 47 (L)).

(10) An etching resist (not shown) was provided for the obtainedsubstrate, and etching was performed by using sulfuric acid-hydrogenperoxide solution. Thus, an opening 44 a having a diameter of 50 μm wasformed in a portion of the electroless copper plating 44 in which viahole would be formed (see FIG. 47 (M)).

(11) The electroless copper plating 44 was used as a conformal mask toirradiate short-pulse (10⁻⁴ second) laser beam (ML605GTL manufactured byMitsubishi Electric). Thus, the adhesive-agent layer 50 below theopening 44 a was removed so that an opening 48 for forming the via holewas formed (see FIG. 47 (N)).

Then, a palladium catalyst (manufactured by Atotech) was attached to thesurface of the circuit board 30 so that a catalyst core was added to thesurface of the electroless-plated film 44 and the coarsened surface ofthe opening 48 for forming the via hole.

(12) The obtained substrate 30 was immersed in the electroless copperplating bath. Thus, an electroless copper plated film 52 having athickness of 1.6 μm was formed on the overall surface of the substrate30 (see FIG. 47 (O)).

(13) Then, a commercial photosensitive dry film (not shown) was appliedto the electroless copper plated film 52. Then, a mask film (not shown)having a pattern printed thereon was placed. The substrate 30 wasexposed to light with 100 mJ/cm², and then a development process wasperformed by using 0.8% sodium carbonate. Thus, a resist 54 having athickness of 15 μm was formed (see FIG. 47 (P)).

(14) The obtained substrate was electrolytic copper plated so that anelectrolytic copper plated film 56 having a thickness of 15 μm wasformed (see FIG. 48 (Q)).

(15) The plating resist 54 was removed by using 5% KOH, and then mixedsolution of sulfuric acid and hydrogen peroxide was used to performetching so that the electroless copper plated film 52 below the platingresist was dissolved and removed. Thus, a conductive circuit 58 and thevia hole 60 composed of the copper foil 32, the electroless plating 44,the electroless plated film 52 and the electrolytic copper plated film56 and having a thickness of 18 μm (10 μm to 30 μm) were obtained (seeFIG. 48 (R)). The thickness was made to be 10 μm to 30 μm tosimultaneously realize a fine pitch and reliability of the connection.

Then, the substrate was immersed in 80 g/L chromic acid at 70° C. for 3minutes to etch the surface of the adhesive-agent layer 50 for theelectroless plating between the conductive circuits 58 by a depthopening 1 μm so as to remove the palladium catalyst on the surface.

(16) A process similar to the process (5) was performed so that acoarsened surface 62 made of Cu—Ni—P was formed on each of the surfaceof the conductive circuit 58 and that of the via hole 60. Then, thesurface was Sn-substituted (see FIG. 48 (S)).

(17) The processes (6) to (16) are repeated so that the upper interlayerinsulating resin layer 160, the via hole 160 and the conductive circuit158 are formed. Then, the coarsened layer 162 is formed on the surfaceof the via hole 160 and that of the conductive circuit 158. Thus, themultilayered printed circuit board is manufactured (see FIG. 47 (T).Note that the Sn substitution was not performed in the process forforming the upper conductive circuit.

(18) Then, a solder bump is formed on the above-mentioned multilayeredprinted circuit board. The two sides of the substrate 30 obtained in theprocess (17) are coated with a solder-resist composition similar to thataccording to the fourth embodiment, the thickness of the solder-resistlayer composition being 45 μm. Then, exposure is performed so that asolder-resist layer (having a thickness of 20 μm) 70 is formed which hasan opening (having a diameter of 200 μm) 71 in the solder pad portion(including the via hole and its land portion) (see FIG. 49 (U)).

(19) Then, the nickel-plated layer 72 having a thickness of 5 μm wasformed in the opening 71. Then, the gold-plated layer 74 having athickness of 0.03 μm is formed on the nickel-plated layer so that thesolder pad 75 is formed on the via hole 160 and the conductive circuit158 (see FIG. 49 (V)).

(22) Solder paste was printed on an opening 71 of the solder-resistlayer 70, followed by performing reflowing at 200° C. Thus, solder bumps(solder) 76U and 76D were formed. As a result, the multilayered printedcircuit board 10 was formed (see FIG. 50).

Comparative Example 8

As a start material for the core substrate, a double-side copper-platedlaminated board which was R-1705 (FR-4 grade: Tg point: 165° C.)manufactured by Matsushita Electrics Works was employed. Similarly tothe sixth embodiment, a multilayered printed circuit board wasmanufactured.

The multilayered printed circuit board according to the sixth embodimentand a multilayered printed circuit board according to a comparativeexample were subjected to the HAST, STEAM and TS tests. Results wereshown in a table shown in FIG. 58.

The HAST test was performed such that 10 multilayered printed circuitboards were used under conditions of 130° C., 85% RH, 1.3 atm, 1.8 Vapplied. The foregoing state was maintained for 10 hours, and theninsulation resistance between plated through holes was measured.

On the other hand, the STEAM test was performed such that 10multilayered printed circuit boards were used such that a state that thetemperature is 121° C. and 100% RH and 2.1 atm was maintained for 336hours to measure the insulation resistance between the plated throughholes.

The TS test was performed such that 10 multilayered printed circuitboards were used such that heating and cooling at −55° C. for threeminutes and 125° C. for three minutes were repeated 1000 times. Thus,change in the resistance in the plated through hole chain was measured.The plated through hole chain is called a chain formed by adjacentthrough holes 36 are electrically connected to one another by theconductive circuits 34 on the right side of the core substrate and theconductive circuits 34 on the reverse side, as shown in FIG. 45 (E′).

As can be understood from the results shown in the table shown in FIG.58, the multilayered printed circuit board according to the comparativeexample encountered considerable deterioration in the insulationcharacteristic.

In the sixth embodiment, the substrate 30 was the R5715 (Tg: 190° C.)manufactured by Matsushita Electrics Works so that the reliabilityrequired as the multilayered printed circuit board was satisfied.Similarly to the sixth embodiment, the following glass epoxy resinsubstrates (1) to (4) having Tg point not lower than 190° C. weresubject to the HAST, STEAM and TS tests. As a result, reliabilitysimilar to that obtainable from the sixth embodiment was realized. Ascan be understood from the foregoing results, use of the glass epoxyresin substrate having Tg point not lower than 190° C. enables therequired reliability to be realized.

(1) Mitsubishi Gas Chemical HL830 (Tg point: 217° C.)(2) Mitsubishi Gas Chemical HL830FC (Tg point: 212° C.)(3) Hitachi Chemical MCL-E-679LD (Tg point 205° C. to 215° C.)(4) Hitachi Chemical MCL-E-679F (Tg point 205° C. to 217° C.)

As described above, the sixth embodiment is structured such that thecore material constituted by a low-cost glass epoxy resin substrate wasemployed as the core substrate. In this embodiment, satisfactoryinsulation resistance between the plated through holes and heat cyclecharacteristic can be realized.

Seventh Embodiment

A printed circuit board and a manufacturing method therefor according toa seventh embodiment will now be described with reference to thedrawings.

As shown in FIG. 53 (B), a printed circuit board 701 according to theseventh embodiment is a so-called double-side board incorporating aninsulation substrate 704 which has, on the right side and reverse sidethereof, a conductor pattern 702 and a plated through hole 703 formed bythe subtractive method. That is, the printed circuit board 701 has twoconductor layers. The insulation substrate 704 is structured such that aglass cloth substrate is impregnated with, for example, epoxy resin,polyimide resin or BT (bis maleimide-triazine) resin. In the seventhembodiment, a substrate (a so-called glass epoxy resin substrate)impregnated with a relatively low-cost epoxy resin is selected. Notethat the insulation substrate 704 is caused from a copper-platedlaminated member 705 which is a metal-plated laminated plate.

The conductor pattern 702 formed on each of the two sides of theinsulation substrate 704 incorporates a copper ground layer 706 having athickness of 0.2 μm to 3.0 μm and serving as a ground layer; a thincopper-plated layer 707 formed on the copper ground layer 706; and athick copper-plated layer 708 formed on the thin copper-plated layer707. That is, the conductor pattern 702 has a three-layered structure.Note that the copper ground layer 706 is caused from a very-thin copperfoil 709 which is very thin conductive metal foil. The space between theadjacent conductor patterns 702 is made to be about 35 μm. The width(the width of the top portion) of the line of the conductor pattern 702is made to be about 70 μm.

The conductor patterns 702 formed on the two sides of the insulationsubstrate 704 are electrically connected to each other through theplated through hole 703 formed to penetrate the insulation substrate704. The conductor layer in the plated through hole 703 incorporates athin copper-plated layer 707 formed on the inner wall of an opening 710for forming the through hole and a thick copper-plated layer 708 formedon the thin copper-plated layer 707. That is, the conductor layer in theplated through hole 703 is formed into a two-layer structure. A land 3 aof the plated through hole 703 has the same structure as that of theconductor pattern 702, that is, the three-layer structure.

The procedure for manufacturing the printed circuit board 701 accordingto the seventh embodiment will now be described.

Initially, the copper-plated laminated member 705 which is themetal-plated laminated board is prepared. As shown in FIG. 51 (A), verythin copper foil 709 is applied to each of the two sides of theinsulation substrate 704 of the copper-plated laminated member 705. Itis preferable that the thickness of the copper foil 709 is 0.5 μm to 7.0μm, more preferably 1.0 μm to 3.0 μm. If the thickness of the copperfoil 709 is too small, handling of the foil deteriorates. Thus, thebonding work cannot easily be completed. If the thickness of the copperfoil 709 is too large, a portion of the thickness which must be removedby etching in a conductor pattern dividing process cannot sufficientlybe reduced. Therefore, this embodiment has the structure that the copperfoil 709 (electrolytic copper foil having a purity of 99.8% or higher)has the thickness of 3.0 μm.

As an alternative to the copper foil 709, metal foil, such as aluminumfoil, tin foil, gold foil, silver foil, platinum foil or nickel foil maybe employed. From a viewpoint of cost reduction and easy etching, it ispreferable that the copper foil 709 is employed similarly to the seventhembodiment.

Then, a drilling process is performed so that an opening 710 for formingthe through hole having a diameter of 0.1 mm to 0.2 μm is formed at apredetermined position of the prepared copper-plated laminated member705 by drilling (see FIG. 51 (B)). When an opening 710 for forming thethrough hole having a smaller diameter is attempted to be formed, alaser work may be performed in place of the drilling work.

When the foregoing opening forming process is performed, smear occurs inthe opening 710 for forming the through hole owing to produced heat. Todissolve and remove produced smear, desmear solution is used to processthe copper-plated laminated member 705. Note that the desmear processmay be performed by a plasma method.

It is preferable that the desmear process is performed under conditionsthat the very thin copper foil 709 does not disappear. Specifically, thedesmear process is performed under condition that the initial thicknessof the copper foil 709 is reduced from 1/10 to ½. In the foregoing case,the desmear solution is solution of sulfuric acid, chromic acid oralkali permanganate. In the seventh embodiment, sodium permanganatesolution having somewhat weak oxidizing power was processed at 30° C. to70° C. for 5 minutes to 20 minutes. The foregoing desmear process hascompletely removed the smear and reduced the initial thickness of thecopper foil 709 to about ⅓. As a result, as shown in FIG. 51 (B), thecopper ground layer 706 caused from the very thin copper foil 709 andhaving a thickness of about 1.0 μm was formed. It is preferable that thethickness of the copper ground layer 706 satisfies a range from 0.2 μmto 3.0 μm.

After the desmear process has been completed, a catalyst core is addedto cause plating to be deposited on the surface of the inner wall of theopening 710 for forming the through hole. Then, the catalyst core isactivated. To add the catalyst core, noble metal ions or noble metalcolloid is employed. In general, palladium chloride or palladium colloidis employed.

After addition of the catalyst core and the process for activating thecatalyst core have been completed, electroless copper plating isperformed to form the thin copper-plated layer 707 on the overallsurface of the copper ground layer 706 and the surface of the inner wallof the opening 710 for forming the through hole (see FIG. 51 (C)).

In a first plating process, an electroless copper plating bath which isone of electroless plating baths is employed so that the thincopper-plated layer 707 having a thickness of 0.5 μm to 2.5 μm isformed. In the seventh embodiment, the thickness of the thincopper-plated layer 707 is made to be about 1.0 μm. If the thickness ofthe thin copper-plated layer 707 is too small, there is apprehensionthat the electrolytic plating cannot reliably be deposited on theoverall surface of the inner wall of the opening 710 for forming thethrough hole in the following plating process. Therefore, there isapprehension that defective conduction of the plated through hole 703occurs and a satisfactory improvement in the reliability cannot berealized. If the thickness of the thin copper-plated layer 707 is toolarge, the productivity deteriorates or the cost is raised. Moreover,there is apprehension that a sufficiently large portion corresponding tothe thickness which must be reduced in the conductor pattern dividingprocess cannot be reduced.

After the first plating process has been completed, a predetermined mask711 which serves as the plating resist is formed on the thincopper-plated layer 707. In the foregoing case, it is preferable thatthe mask 711 is formed by using a commercial dry film photoresist. Thereason for this lies in that use of the photosensitive material willcontribute to an improvement in the accuracy of formation of thepattern. The foregoing dry film photoresist is laminated, and thenexposure and development are performed by usual methods. As a result, asshown in FIG. 52 (A), the mask 711 having the opening 712 at apredetermined position thereof and a thickness of 35 μm is formed.

After the process for forming the mask has been completed, electrolyticcopper plating bath which is one of the electrolytic plating is used toform the thick copper-plated layer 708 in the portion exposed over theopening 712 (see FIG. 52 (B)). When the foregoing thick copper-platedlayer 708 is formed, only the portion which will be formed into theconductor pattern 702 is selectively thickened. As the electrolyticcopper plating bath, a copper sulfate plating bath is employed in theseventh embodiment. As a result of the second plating process, the thickcopper-plated layer 708 having a thickness of about 15 μmm to about 50μm is formed on the thin copper-plated layer 707 positioned at theexposed position. If the thickness of the thick copper-plated layer 708is too small, a required thickness of the conductor pattern 702 whichwill finally be obtained cannot be maintained. If the thickness of thethick copper-plated layer 708 is too large, there is apprehension thatthe productivity deteriorates and the cost is raised excessively. In theseventh embodiment, the thickness of the thick copper-plated layer 708is made to be about 20 μm.

After the second plating process has been completed, the mask 711 whichhas been made to be unnecessary is separated. Thus, the thincopper-plated layer 707 positioned below the mask 711 is exposed (seeFIG. 53 (A)). An etchant which is capable of dissolving copper is usedto perform an etching process so that the thin copper-plated layer 707and the copper ground layer 706 are completely removed. In thisembodiment, the process is performed such that no etching resist isprovided on the thick copper-plated layer 708. Therefore, the uppermostlayer of the thick copper-plated layer 708 is also etched by about 2 μm.As a result of the foregoing process, the conductor pattern 702 isdivided so that the printed circuit board 701 shown in FIG. 53 (B) ismanufactured.

Therefore, the seventh embodiment attains the following effects.

(1) Both of the thicknesses of the thin copper-plated layer 707 and thecopper ground layer 706 can considerably be reduced. Therefore, thethickness which must be removed by etching in the conductor patterndividing process can considerably be reduced to about 2 μm as comparedwith the conventional technique. Therefore, the conductor pattern 702formed owing to the dividing process is not formed into the divergentshape. As a result, a fine pattern having a satisfactory shape canaccurately be formed.

(2) The electroless copper plating bath is employed in the first platingprocess and the electrolytic copper plating bath is employed in thesecond plating process so that the printed circuit board 701 ismanufactured. Namely, the electroless copper plating bath is employedonly when plating is deposited on the surface of the inner wall of theopening 710 for forming the through hole. Then, very low-costelectrolytic copper plating bath with which the depositing speed can beraised is employed. As a result, the cost reduction and improvement inthe productivity can be realized.

Since the very thin copper-plated layer 707 can be formed, the thicknesswhich must be removed in the process for dividing the conductor patterncan considerably be reduced. Therefore, the foregoing selection of theplating bath reliably contributes to furthermore the accurate formationof a fine pattern having a satisfactory shape.

(3) The process for dividing the conductor pattern in the seventhembodiment is performed by etching which is performed such that noetching resist is disposed on the thick copper-plated layer 708.Therefore, the process for forming and separating the etching resist inthe foregoing process can basically be omitted. As a result, the numberof processes can be reduced, causing the productivity to furthermore beimproved. Moreover, the thickness of the thick copper-plated layer 708which must be reduced by etching is considerably reduced to about 2 μm.Multilayered printed circuit boards result, if the etching process isperformed, no adverse influence is exerted on the accuracy of the formedpattern and cost reduction.

(4) The printed circuit board 701 obtained by the foregoingmanufacturing method incorporates the conductor pattern 702 whichincorporates the copper ground layer 706 caused from the copper foil 709and having the thickness of about 1.0 μm, the thick copper-plated layer708 having the thickness of about 1.0 μm and the thick copper-platedlayer 708 having the thickness of 20 μm. The metal materials whichconstitute the three layers are the same (that is, copper).

The foregoing conductor pattern 702, serving as the conductor portion,has a sufficiently large thickness, an excellent shape and satisfactoryconduction characteristic. Moreover, another advantage can be realizedin that satisfactory reliability is obtained.

(5) In the seventh embodiment, the copper-plated laminated member 705incorporates the insulation substrate 704 to which the copper foil 709having a thickness of 0.5 μm to 7.0 μm is bonded to each side thereof.Thus, the printed circuit board 701 is manufactured. When the foregoingcopper-plated laminated member 705 is employed, the soft desmear processis able to completely remove the smear. Moreover, the copper groundlayer 706 having a preferred thickness can easily and reliably beformed. Therefore, the copper-plated laminated member 705 is asatisfactory material when an excellent printed circuit board 701 isobtained by the foregoing method.

Note that the seventh embodiment may be changed as follows.

The seventh embodiment is not limited to the foregoing double-sideboard. For example, the printed circuit board 701 according to theembodiment may be used as the core substrate to manufacture amultilayered printed circuit board 21 according to a first modificationshown in FIG. 54. The printed circuit board 701 may be used as the basesubstrate to manufacture a built-up and multilayered printed circuitboard 31 according to a second modification shown in FIG. 9.

A variety of metal-plated laminated board to which, for example,aluminum foil, tin foil, gold foil, silver foil, platinum foil or nickelfoil except for the copper-plated laminated member 705 is applied may beused to manufacture the printed circuit board 701.

As an alternative to the wet method according to the seventh embodiment,the desmear process may be performed by a dry method which isrepresented by, for example, a plasma method.

In the first plating process, the electroless plating bath except forthe electroless copper plating bath may be employed to form a thinelectroless solder plating layer, electroless gold plating layer orelectroless palladium plating layer.

In the second embodiment, an electrolytic plating bath except for theelectrolytic copper plating bath may be employed to form a thickelectroless nickel plating layer, electroless plating chrome platinglayer or electroless gold plating layer.

The thin electroless plating layer, the thick electrolytic plating layerand the ground layer are not always required to be made of the samemetal material. Different metal materials may be combined with oneanother.

In addition to the technical ideas claimed in claims, technical ideasobtainable from the foregoing embodiments and attained effects will nowbe described if necessary.

(1) A printed circuit board having a conductor pattern (formed by, forexample, the subtractive method or the like) incorporates a copperground layer which is caused from copper foil bonded to an insulatingsubstrate and having a thickness of 0.5 μm to 7.0 μm and which has athickness of 0.2 μm to 2.5 μm; and a thick electrolytic copper platedlayer formed on the thin electroless copper plated layer and a thicknessof 8.0 μm or greater. Therefore, the invention described in thetechnical idea 1 is able to provide a dense printed circuit boardexhibiting excellent reliability, low cost and pattern formationaccuracy.

(2) A multilayered printed circuit board incorporating a printed circuitboard disclosed in any one of the technical idea 1 as a core substrate.Therefore, according to the invention described in the technical idea 2,a dense printed circuit board exhibiting excellent reliability, lowcost, pattern formation accuracy and improved function can be provided.

(3) A built-up multilayered printed circuit board incorporating theprinted circuit board described in any one of the technical idea 1 asthe base substrate. Therefore, according to the invention described inthe technical idea 3, a dense printed circuit board exhibiting excellentreliability, low cost, pattern formation accuracy and improved functioncan be provided.

(4) A copper-plated laminated board formed by bonding copper foil havinga thickness of 0.5 μm to 7.0 μm to each of the two sides of aninsulating substrate. Therefore, according to the inventions describedin the technical idea 4, a preferred material for obtaining theexcellent printed circuit board by the foregoing manufacturing methodcan be provided.

(5) A copper-plated laminated board formed by bonding copper foil havinga thickness of 1.0 μm to 3.0 μm to each of the two sides of a glasscloth substrate impregnated with epoxy resin, polyimide resin or BTresin. Therefore, according to the invention described in the technicalidea 5, a preferred material for obtaining the excellent printed circuitboard by the foregoing manufacturing method can be provided.

(6) With either of the technical ideas 1 and 2, the desmear process isperformed such that the desmear solution is processed under a conditionthat the conductive metal foil does not disappear.

(7) The desmear process is performed such that the desmear solution isprocessed under condition that the initial thickness of the conductivemetal foil is reduced from 1/10 to ½.

(8) A printed circuit board having a conductor pattern formed by thesubtractive method, wherein the conductor pattern incorporates a groundlayer caused from very thin conductive metal foil, which is bonded to aninsulating substrate, and having a thickness of 0.2 μm to 2.0 μm; and aplated layer formed on the ground layer.

(9) A printed circuit board having a conductor pattern formed by thesubtractive method, wherein the conductor pattern incorporates a groundlayer, which is caused from conductive metal foil bonded to aninsulating substrate and which has a thickness of 0.5 μm to 5.0 μm, andwhich has a thickness of 0.2 μm to 2.0 μm; and a thick plated layerformed on the thin plated layer.

1. A multilayered printed circuit board comprising: a substrate on whicha conductive circuit is formed; an interlayer insulating resin layerformed on the conductive circuit; an opening for forming a via holeformed in the interlayer insulating resin layer; and another conductivecircuit including a via hole and formed on the interlayer insulatingresin layer, wherein the surface of the conductive circuit is subjectedto a coarsening process using etching solution containing cupric complexand organic acid, and stripe pits and projections are formed on theinner wall of the opening for forming the via hole.
 2. A method ofmanufacturing a multilayered printed circuit board including (1) a stepof forming a conductive circuit; (2) a step of forming an interlayerinsulating resin layer on the conductive circuit; (3) a step of applyinga laser beam to form an opening for forming a via hole in the interlayerinsulating resin layer; and (4) a step of forming another conductivecircuit including a via hole on the interlayer insulating resin layer,wherein the surface of the conductive circuit is subjected to acoarsening process by using etching solution containing cupric complexand organic acid.
 3. A method of manufacturing a multilayered printedcircuit board according to claim 1, wherein the etching solutioncontaining the cupric complex and the organic acid is sprayed to thesurface of the conductive circuit or the conductive circuit is immersedin the etching solution under a bubbling condition so that the surfaceof the conductive circuit is subjected to the coarsening process.
 4. Amethod of manufacturing a multilayered printed circuit board comprisingat least the steps (a) to (d): (a) forming a conductive circuit; (b)coating the conductive circuit with resin; (c) irradiating the resinwith a carbon-dioxide gas laser beam to form a through hole whichreaches the conductive circuit such that the carbon-dioxide gas laserbeam is vertically applied to the conductive circuit below the resin tocause interference of reflected wave from the conductive circuit andincident wave to occur so that stripe pits and projections are formed onthe side wall of the through hole; and (d) coating the through hole withmetal to form a via hole.
 5. A method of manufacturing a multilayeredprinted circuit board according to claim 4, wherein the resin isthermosetting resin or a composite material of the thermosetting resinand thermoplastic resin.
 6. A method of manufacturing a multilayeredprinted circuit board according to claim 4 or 5, wherein the step offorming the via hole includes a step of forming a resist after anelectroless copper plated film has been formed in the through hole andsupplying electric power through the electroless plated film to form anelectrolytic plated film in a portion in which the resist is not formed.7. A multilayered printed circuit board according to any one of claims 4to 6, wherein the interlayer insulating resin layer contains acrylicmonomer.
 8. A method of manufacturing a printed circuit board comprisingat least the steps (a) and (b): (a) forming a solder-resist layer on thesurface of a substrate on which a conductive circuit has been formed;and (b) irradiating the solder-resist layer with a laser beam to form athrough hole which reaches the conductive circuit.
 9. A method ofmanufacturing a printed circuit board according to claim 8, wherein thesurface of the conductive circuit has a metal coarsened layer.
 10. Amethod of manufacturing printed circuit board according to claim 8,wherein (c) a step of forming a bump made metal having a low meltingpoint in the through hole is performed after the step (b).
 11. A methodof manufacturing printed circuit board according to claim 8, wherein alaser beam in a single mode is applied in the step of forming thethrough hole so that a through hole having a diameter of 300 μm to 650μm is formed.
 12. A method of manufacturing printed circuit boardaccording to claim 8 wherein a laser beam in a multi mode is applied inthe step of forming the through hole so that a through hole having adiameter of 50 μm to 300 μm is formed.
 13. A method of manufacturing aprinted circuit board according to any one of claims 8 to 12, whereinthe step of forming the through hole is performed such that thecarbon-dioxide gas laser beam is vertically applied to the conductivecircuit below the resin to cause interference of reflected wave from theconductive circuit and incident wave to occur so that stripe pits andprojections are formed on the side wall of the through hole.
 14. Amethod of manufacturing a printed circuit board according to claim 13,wherein the step of forming the bump is performed such that a metal filmis provided for the through hole having the side wall provided with thestripe pits and projections, and then metal having a low melting pointis enclosed.
 15. A method of manufacturing a multilayered printedcircuit board such that a through hole is formed in a double-sidecopper-plated laminated board by performing a laser machining and thethrough hole is made to be conductive to form a through hole so that acore substrate is manufactured, and an interlayer insulating resin layerand a conductive circuit are formed on the core substrate, said methodof manufacturing a multilayered printed circuit board comprising thestep of: making the thickness of copper foil of the double-sidecopper-plated laminated board to be smaller than 12 μm.
 16. A method ofmanufacturing a multilayered printed circuit board according to claim15, wherein the laser machining uses a carbon-dioxide gas laser beam.17. A method of manufacturing a multilayered printed circuit boardaccording to claim 15 or 16, wherein the laser machining usesshort-pulse carbon-dioxide gas laser beam of 20 mJ to 40 mJ and 10⁻⁴second to 10⁻⁸ second.
 18. A method of manufacturing a printed circuitboard incorporating through holes and conductor patterns formed by asubtractive method, said method of manufacturing a printed circuit boardcomprising: an opening forming step for forming an opening for forming athrough hole at a predetermined position of a metal-applied board formedby applying-conductive metal foil having a thickness of 0.5 μm to 7.0 μmto each of two sides of an insulating substrate; a desmear step fordissolving and removing smear existing in the opening for forming thethrough hole; a first plating step for forming a thin plated layer on aground layer caused from the conductive metal foil and the surface ofthe inner wall of the opening for forming the through hole; a secondplating step for forming a mask on the thin plated layer and forming athick plated layer on a portion exposed through an opening of the mask;and performing etching after the mask has been separated so that thethin plated layer and the ground layer below the mask are removed so asto divide the conductor patter.
 19. A method of manufacturing a printedcircuit board according to claim 18, wherein the conductive metal foilincluding at least one of Cu, Ni, Sn, Au, Ag, Pt or Al.
 20. A method ofmanufacturing a printed circuit board according to claim 18, wherein thefirst plating step uses an electroless plating bath, and the secondplating step uses an electrolytic plating bath.
 21. A method ofmanufacturing a printed circuit board according to claim 18, wherein thefirst plating step uses an electroless copper plating bath to form acopper plated layer having a thickness of 0.2 μm to 2.5 μm, and thesecond plating step uses an electrolytic copper plating bath to form acopper plated layer having a thickness of 8.0 μm or greater.
 22. Amethod of manufacturing a printed circuit board according to any one ofclaims 18 to 21, wherein the step for dividing the conductor pattern byperforming etching is performed in a state in which no etching resist isprovided for the thick plated layer formed in the second plating step.